[MIPS] N32: Make sure pointer is good before passing it to sys_waitid().

[powerpc.git] / arch / mips / kernel / time.c

diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 0dd0df7..7050b4f 100644 (file)
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -25,6 +26,7 @@
 #include <linux/module.h>
 
 #include <asm/bootinfo.h>
+#include <asm/cache.h>
 #include <asm/compiler.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
@@ -43,10 +45,6 @@
 
 #define TICK_SIZE      (tick_nsec / 1000)
 
-u64 jiffies_64 = INITIAL_JIFFIES;
-
-EXPORT_SYMBOL(jiffies_64);
-
 /*
  * forward reference
  */
@@ -76,7 +74,7 @@ int (*rtc_set_mmss)(unsigned long);
 static unsigned int sll32_usecs_per_cycle;
 
 /* how many counter cycles in a jiffy */
-static unsigned long cycles_per_jiffy;
+static unsigned long cycles_per_jiffy __read_mostly;
 
 /* Cycle counter value at the previous timer interrupt.. */
 static unsigned int timerhi, timerlo;
@@ -98,7 +96,10 @@ static unsigned int null_hpt_read(void)
        return 0;
 }
 
-static void null_hpt_init(unsigned int count) { /* nothing */ }
+static void null_hpt_init(unsigned int count)
+{
+       /* nothing */
+}
 
 
 /*
@@ -108,8 +109,10 @@ static void c0_timer_ack(void)
 {
        unsigned int count;
 
+#ifndef CONFIG_SOC_PNX8550     /* pnx8550 resets to zero */
        /* Ack this timer interrupt and set the next one.  */
        expirelo += cycles_per_jiffy;
+#endif
        write_c0_compare(expirelo);
 
        /* Check to see if we have missed any timer interrupts.  */
@@ -224,7 +227,6 @@ int do_settimeofday(struct timespec *tv)
        set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
 
        ntp_clear();
-
        write_sequnlock_irq(&xtime_lock);
        clock_was_set();
        return 0;
@@ -505,14 +507,38 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
        return IRQ_HANDLED;
 }
 
+int null_perf_irq(struct pt_regs *regs)
+{
+       return 0;
+}
+
+int (*perf_irq)(struct pt_regs *regs) = null_perf_irq;
+
+EXPORT_SYMBOL(null_perf_irq);
+EXPORT_SYMBOL(perf_irq);
+
 asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
 {
+       int r2 = cpu_has_mips_r2;
+
        irq_enter();
        kstat_this_cpu.irqs[irq]++;
 
+       /*
+        * Suckage alert:
+        * Before R2 of the architecture there was no way to see if a
+        * performance counter interrupt was pending, so we have to run the
+        * performance counter interrupt handler anyway.
+        */
+       if (!r2 || (read_c0_cause() & (1 << 26)))
+               if (perf_irq(regs))
+                       goto out;
+
        /* we keep interrupt disabled all the time */
-       timer_interrupt(irq, NULL, regs);
+       if (!r2 || (read_c0_cause() & (1 << 30)))
+               timer_interrupt(irq, NULL, regs);
 
+out:
        irq_exit();
 }
 
@@ -626,9 +652,9 @@ void __init time_init(void)
                        mips_hpt_init = c0_hpt_init;
                }
 
-               if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) ||
-                        (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
-                        (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
+               if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
+                   (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
+                   (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
                        /*
                         * We need to calibrate the counter but we don't have
                         * 64-bit division.