[PATCH] powerpc: fix various sparse warnings

[powerpc.git] / arch / powerpc / kernel / head_32.S

diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 108e78e..a0579e8 100644 (file)
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -120,10 +120,25 @@ __start:
  * because OF may have I/O devices mapped into that area
  * (particularly on CHRP).
  */
+#ifdef CONFIG_PPC_MULTIPLATFORM
        cmpwi   0,r5,0
        beq     1f
        bl      prom_init
        trap
+#endif
+
+/*
+ * Check for BootX signature when supporting PowerMac and branch to
+ * appropriate trampoline if it's present
+ */
+#ifdef CONFIG_PPC_PMAC
+1:     lis     r31,0x426f
+       ori     r31,r31,0x6f58
+       cmpw    0,r3,r31
+       bne     1f
+       bl      bootx_init
+       trap
+#endif /* CONFIG_PPC_PMAC */
 
 1:     mr      r31,r3                  /* save parameters */
        mr      r30,r4
@@ -210,7 +225,7 @@ turn_on_mmu:
        .globl  __secondary_hold
 __secondary_hold:
        /* tell the master we're here */
-       stw     r3,4(0)
+       stw     r3,__secondary_hold_acknowledge@l(0)
 #ifdef CONFIG_SMP
 100:   lwz     r4,0(0)
        /* wait until we're told to start */
@@ -223,6 +238,13 @@ __secondary_hold:
        b       .
 #endif /* CONFIG_SMP */
 
+       .globl  __secondary_hold_spinloop
+__secondary_hold_spinloop:
+       .long   0
+       .globl  __secondary_hold_acknowledge
+__secondary_hold_acknowledge:
+       .long   -1
+
 /*
  * Exception entry code.  This code runs with address translation
  * turned off, i.e. using physical addresses.
@@ -267,6 +289,9 @@ __secondary_hold:
        li      r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
        MTMSRD(r10);                    /* (except for mach check in rtas) */ \
        stw     r0,GPR0(r11);   \
+       lis     r10,0x7265;             /* put exception frame marker */ \
+       addi    r10,r10,0x6773; \
+       stw     r10,8(r11);     \
        SAVE_4GPRS(3, r11);     \
        SAVE_2GPRS(7, r11)
 
@@ -290,7 +315,7 @@ label:                                              \
 
 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret)    \
        li      r10,trap;                                       \
-       stw     r10,TRAP(r11);                                  \
+       stw     r10,_TRAP(r11);                                 \
        li      r10,MSR_KERNEL;                                 \
        copyee(r10, r9);                                        \
        bl      tfer;                                           \
@@ -443,16 +468,11 @@ SystemCall:
  * by executing an altivec instruction.
  */
        . = 0xf00
-       b       Trap_0f
+       b       PerformanceMonitor
 
        . = 0xf20
        b       AltiVecUnavailable
 
-Trap_0f:
-       EXCEPTION_PROLOG
-       addi    r3,r1,STACK_FRAME_OVERHEAD
-       EXC_XFER_EE(0xf00, unknown_exception)
-
 /*
  * Handle TLB miss for instruction on 603/603e.
  * Note: we get an alternate set of r0 - r3 to use automatically.
@@ -694,8 +714,14 @@ AltiVecUnavailable:
 #ifdef CONFIG_ALTIVEC
        bne     load_up_altivec         /* if from user, just load it up */
 #endif /* CONFIG_ALTIVEC */
+       addi    r3,r1,STACK_FRAME_OVERHEAD
        EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
 
+PerformanceMonitor:
+       EXCEPTION_PROLOG
+       addi    r3,r1,STACK_FRAME_OVERHEAD
+       EXC_XFER_STD(0xf00, performance_monitor_exception)
+
 #ifdef CONFIG_ALTIVEC
 /* Note that the AltiVec support is closely modeled after the FP
  * support.  Changes to one are likely to be applicable to the
@@ -834,10 +860,10 @@ relocate_kernel:
  * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
  * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
  */
-copy_and_flush:
+_GLOBAL(copy_and_flush)
        addi    r5,r5,-4
        addi    r6,r6,-4
-4:     li      r0,L1_CACHE_LINE_SIZE/4
+4:     li      r0,L1_CACHE_BYTES/4
        mtctr   r0
 3:     addi    r6,r6,4                 /* copy a cache line */
        lwzx    r0,r6,r4
@@ -1093,6 +1119,7 @@ start_here:
        mr      r3,r31
        mr      r4,r30
        bl      machine_init
+       bl      __save_cpu_setup
        bl      MMU_init
 
 #ifdef CONFIG_APUS
@@ -1297,6 +1324,7 @@ initial_bats:
        isync
        blr
 
+
 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
 setup_disp_bat:
        /*
@@ -1307,6 +1335,8 @@ setup_disp_bat:
        mtlr    r8
        addis   r8,r3,disp_BAT@ha
        addi    r8,r8,disp_BAT@l
+       cmpwi   cr0,r8,0
+       beqlr
        lwz     r11,0(r8)
        lwz     r8,4(r8)
        mfspr   r9,SPRN_PVR
@@ -1319,10 +1349,8 @@ setup_disp_bat:
 1:     mtspr   SPRN_IBAT3L,r8
        mtspr   SPRN_IBAT3U,r11
        blr
-
 #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
 
-
 #ifdef CONFIG_8260
 /* Jump into the system reset for the rom.
  * We first disable the MMU, and then jump to the ROM reset address.