Merge branch 'master'

[powerpc.git] / arch / ppc / syslib / ppc4xx_pic.c

diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c
index 08f06dd..0b43563 100644 (file)
--- a/arch/ppc/syslib/ppc4xx_pic.c
+++ b/arch/ppc/syslib/ppc4xx_pic.c
@@ -25,6 +25,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/ppc4xx_pic.h>
+#include <asm/machdep.h>
 
 /* See comment in include/arch-ppc/ppc4xx_pic.h
  * for more info about these two variables
@@ -41,7 +42,10 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
 #define UIC_HANDLERS(n)                                                        \
 static void ppc4xx_uic##n##_enable(unsigned int irq)                   \
 {                                                                      \
-       ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq);                 \
+       u32 mask = IRQ_MASK_UIC##n(irq);                                \
+       if (irq_desc[irq].status & IRQ_LEVEL)                           \
+               mtdcr(DCRN_UIC_SR(UIC##n), mask);                       \
+       ppc_cached_irq_mask[n] |= mask;                                 \
        mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);             \
 }                                                                      \
                                                                        \
@@ -107,6 +111,10 @@ static int ppc4xx_pic_get_irq(struct pt_regs *regs)
 
 static void __init ppc4xx_pic_impl_init(void)
 {
+#if defined(CONFIG_440GX)
+       /* Disable 440GP compatibility mode if it was enabled in firmware */
+       SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM);
+#endif
        /* Configure Base UIC */
        mtdcr(DCRN_UIC_CR(UICB), 0);
        mtdcr(DCRN_UIC_TR(UICB), 0);