#include <linux/libata.h>
#define DRV_NAME "pata_hpt37x"
-#define DRV_VERSION "0.6.4"
+#define DRV_VERSION "0.6.5"
struct hpt_clock {
u8 xfer_speed;
hpt37x_timings_33,
NULL,
NULL,
- hpt37x_timings_66
+ NULL
}
};
hpt37x_timings_33,
NULL,
hpt37x_timings_50,
- hpt37x_timings_66
+ NULL
}
};
/**
* hpt37x_pre_reset - reset the hpt37x bus
* @ap: ATA port to reset
+ * @deadline: deadline jiffies for the operation
*
* Perform the initial reset handling for the 370/372 and 374 func 0
*/
-static int hpt37x_pre_reset(struct ata_port *ap)
+static int hpt37x_pre_reset(struct ata_port *ap, unsigned long deadline)
{
u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
- return ata_std_prereset(ap);
+ return ata_std_prereset(ap, deadline);
}
/**
ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}
-static int hpt374_pre_reset(struct ata_port *ap)
+static int hpt374_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits hpt37x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
- return ata_std_prereset(ap);
+ return ata_std_prereset(ap, deadline);
}
/**
return -ENODEV;
port = &info_hpt372;
chip_table = &hpt371;
- /* Single channel device, paster is not present
- but the NIOS (or us for non x86) must mark it
+ /* Single channel device, master is not present
+ but the BIOS (or us for non x86) must mark it
absent */
pci_read_config_byte(dev, 0x50, &mcr1);
mcr1 &= ~0x04;
} else {
port->private_data = (void *)chip_table->clocks[clock_slot];
/*
- * Perform a final fixup. The 371 and 372 clock determines
- * if UDMA133 is available. (FIXME: should we use DPLL then ?)
- */
+ * Perform a final fixup. Note that we will have used the
+ * DPLL on the HPT372 which means we don't have to worry
+ * about lack of UDMA133 support on lower clocks
+ */
- if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
- printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
- if (port == &info_hpt372)
- port = &info_hpt372_50;
- else BUG();
- }
if (clock_slot < 2 && port == &info_hpt370)
port = &info_hpt370_33;
if (clock_slot < 2 && port == &info_hpt370a)