#include <asm/uaccess.h>
#include <asm/system.h>
-/* If the kernel parameter wdt_enable=1, the watchdog will be enabled at boot.
+/* If the kernel parameter wdt=1, the watchdog will be enabled at boot.
* Also, the wdt_period sets the watchdog timer period timeout.
* For E500 cpus the wdt_period sets which bit changing from 0->1 will
* trigger a watchog timeout. This watchdog timeout will occur 3 times, the
#ifdef CONFIG_FSL_BOOKE
#define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */
#else
-#define WDT_PERIOD_DEFAULT 4 /* Refer to the PPC40x and PPC4xx manuals */
+#define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */
#endif /* for timing information */
u32 booke_wdt_enabled = 0;
#define WDTP(x) (TCR_WP(x))
#endif
+/*
+ * booke_wdt_ping:
+ */
+static __inline__ void booke_wdt_ping(void)
+{
+ mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
+}
+
/*
* booke_wdt_enable:
*/
{
u32 val;
+ /* clear status before enabling watchdog */
+ booke_wdt_ping();
val = mfspr(SPRN_TCR);
val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period));
mtspr(SPRN_TCR, val);
}
-/*
- * booke_wdt_ping:
- */
-static __inline__ void booke_wdt_ping(void)
-{
- mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
-}
-
/*
* booke_wdt_write:
*/
return -EINVAL;
return 0;
default:
- return -ENOIOCTLCMD;
+ return -ENOTTY;
}
return 0;
booke_wdt_period);
}
- return 0;
+ return nonseekable_open(inode, file);
}
static const struct file_operations booke_wdt_fops = {