[MTD] NAND: S3C2410 convert prinks to dev_*()s

[powerpc.git] / drivers / mtd / nand / edb7312.c

diff --git a/drivers/mtd/nand/edb7312.c b/drivers/mtd/nand/edb7312.c
index 8467d77..516c0e5 100644 (file)
--- a/drivers/mtd/nand/edb7312.c
+++ b/drivers/mtd/nand/edb7312.c
@@ -1,7 +1,7 @@
 /*
  *  drivers/mtd/nand/edb7312.c
  *
- *  Copyright (C) 2002 Marius Gröger (mag@sysgo.de)
+ *  Copyright (C) 2002 Marius Gröger (mag@sysgo.de)
  *
  *  Derived from drivers/mtd/nand/autcpu12.c
  *       Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
@@ -73,32 +73,26 @@ static struct mtd_partition partition_info[] = {
 
 /*
  *     hardware specific access to control-lines
+ *
+ *     NAND_NCE: bit 0 -> bit 7
+ *     NAND_CLE: bit 1 -> bit 4
+ *     NAND_ALE: bit 2 -> bit 5
  */
-static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd)
+static void ep7312_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-       switch (cmd) {
-
-       case NAND_CTL_SETCLE:
-               clps_writeb(clps_readb(ep7312_pxdr) | 0x10, ep7312_pxdr);
-               break;
-       case NAND_CTL_CLRCLE:
-               clps_writeb(clps_readb(ep7312_pxdr) & ~0x10, ep7312_pxdr);
-               break;
-
-       case NAND_CTL_SETALE:
-               clps_writeb(clps_readb(ep7312_pxdr) | 0x20, ep7312_pxdr);
-               break;
-       case NAND_CTL_CLRALE:
-               clps_writeb(clps_readb(ep7312_pxdr) & ~0x20, ep7312_pxdr);
-               break;
-
-       case NAND_CTL_SETNCE:
-               clps_writeb((clps_readb(ep7312_pxdr) | 0x80) & ~0x40, ep7312_pxdr);
-               break;
-       case NAND_CTL_CLRNCE:
-               clps_writeb((clps_readb(ep7312_pxdr) | 0x80) | 0x40, ep7312_pxdr);
-               break;
+       struct nand_chip *chip = mtd->priv;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               unsigned char bits;
+
+               bits = (ctrl & (NAND_CLE | NAND_ALE)) << 3;
+               bits = (ctrl & NAND_NCE) << 7;
+
+               clps_writeb((clps_readb(ep7312_pxdr)  & 0xB0) | 0x10,
+                           ep7312_pxdr);
        }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, chip->IO_ADDR_W);
 }
 
 /*
@@ -148,6 +142,7 @@ static int __init ep7312_init(void)
 
        /* Link the private data with the MTD structure */
        ep7312_mtd->priv = this;
+       ep7312_mtd->owner = THIS_MODULE;
 
        /*
         * Set GPIO Port B control register so that the pins are configured
@@ -158,7 +153,7 @@ static int __init ep7312_init(void)
        /* insert callbacks */
        this->IO_ADDR_R = ep7312_fio_base;
        this->IO_ADDR_W = ep7312_fio_base;
-       this->hwcontrol = ep7312_hwcontrol;
+       this->cmd_ctrl = ep7312_hwcontrol;
        this->dev_ready = ep7312_device_ready;
        /* 15 us command delay time */
        this->chip_delay = 15;
@@ -203,9 +198,6 @@ static void __exit ep7312_cleanup(void)
        /* Release resources, unregister device */
        nand_release(ap7312_mtd);
 
-       /* Free internal data buffer */
-       kfree(this->data_buf);
-
        /* Free the MTD device structure */
        kfree(ep7312_mtd);
 }