* $Id: nandsim.c,v 1.8 2005/03/19 15:33:56 dedekind Exp $
*/
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
-#ifdef CONFIG_NS_ABS_POS
-#include <asm/io.h>
-#endif
-
/* Default simulator parameters values */
#if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
/* Initialize the NAND flash parameters */
ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
ns->geom.totsz = mtd->size;
- ns->geom.pgsz = mtd->oobblock;
+ ns->geom.pgsz = mtd->writesize;
ns->geom.oobsz = mtd->oobsize;
ns->geom.secsz = mtd->erasesize;
ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
printk("options: %#x\n", ns->options);
/* Map / allocate and initialize the flash image */
-#ifdef CONFIG_NS_ABS_POS
- ns->mem.byte = ioremap(CONFIG_NS_ABS_POS, ns->geom.totszoob);
- if (!ns->mem.byte) {
- NS_ERR("init_nandsim: failed to map the NAND flash image at address %p\n",
- (void *)CONFIG_NS_ABS_POS);
- return -ENOMEM;
- }
-#else
ns->mem.byte = vmalloc(ns->geom.totszoob);
if (!ns->mem.byte) {
NS_ERR("init_nandsim: unable to allocate %u bytes for flash image\n",
return -ENOMEM;
}
memset(ns->mem.byte, 0xFF, ns->geom.totszoob);
-#endif
/* Allocate / initialize the internal buffer */
ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
return 0;
error:
-#ifdef CONFIG_NS_ABS_POS
- iounmap(ns->mem.byte);
-#else
vfree(ns->mem.byte);
-#endif
return -ENOMEM;
}
free_nandsim(struct nandsim *ns)
{
kfree(ns->buf.byte);
-
-#ifdef CONFIG_NS_ABS_POS
- iounmap(ns->mem.byte);
-#else
vfree(ns->mem.byte);
-#endif
return;
}
}
}
-static void
-ns_hwcontrol(struct mtd_info *mtd, int cmd)
-{
- struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
-
- switch (cmd) {
-
- /* set CLE line high */
- case NAND_CTL_SETCLE:
- NS_DBG("ns_hwcontrol: start command latch cycles\n");
- ns->lines.cle = 1;
- break;
-
- /* set CLE line low */
- case NAND_CTL_CLRCLE:
- NS_DBG("ns_hwcontrol: stop command latch cycles\n");
- ns->lines.cle = 0;
- break;
-
- /* set ALE line high */
- case NAND_CTL_SETALE:
- NS_DBG("ns_hwcontrol: start address latch cycles\n");
- ns->lines.ale = 1;
- break;
-
- /* set ALE line low */
- case NAND_CTL_CLRALE:
- NS_DBG("ns_hwcontrol: stop address latch cycles\n");
- ns->lines.ale = 0;
- break;
-
- /* set WP line high */
- case NAND_CTL_SETWP:
- NS_DBG("ns_hwcontrol: enable write protection\n");
- ns->lines.wp = 1;
- break;
-
- /* set WP line low */
- case NAND_CTL_CLRWP:
- NS_DBG("ns_hwcontrol: disable write protection\n");
- ns->lines.wp = 0;
- break;
-
- /* set CE line low */
- case NAND_CTL_SETNCE:
- NS_DBG("ns_hwcontrol: enable chip\n");
- ns->lines.ce = 1;
- break;
-
- /* set CE line high */
- case NAND_CTL_CLRNCE:
- NS_DBG("ns_hwcontrol: disable chip\n");
- ns->lines.ce = 0;
- break;
-
- default:
- NS_ERR("hwcontrol: unknown command\n");
- }
-
- return;
-}
-
static u_char
ns_nand_read_byte(struct mtd_info *mtd)
{
return;
}
+static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
+{
+ struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
+
+ ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
+ ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
+ ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
+
+ if (cmd != NAND_CMD_NONE)
+ ns_nand_write_byte(mtd, cmd);
+}
+
static int
ns_device_ready(struct mtd_info *mtd)
{
return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
}
-static void
-ns_nand_write_word(struct mtd_info *mtd, uint16_t word)
-{
- struct nand_chip *chip = (struct nand_chip *)mtd->priv;
-
- NS_DBG("write_word\n");
-
- chip->write_byte(mtd, word & 0xFF);
- chip->write_byte(mtd, word >> 8);
-}
-
static void
ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
/*
* Module initialization function
*/
-int __init ns_init_module(void)
+static int __init ns_init_module(void)
{
struct nand_chip *chip;
struct nandsim *nand;
/*
* Register simulator's callbacks.
*/
- chip->hwcontrol = ns_hwcontrol;
+ chip->cmd_ctrl = ns_hwcontrol;
chip->read_byte = ns_nand_read_byte;
chip->dev_ready = ns_device_ready;
- chip->write_byte = ns_nand_write_byte;
chip->write_buf = ns_nand_write_buf;
chip->read_buf = ns_nand_read_buf;
chip->verify_buf = ns_nand_verify_buf;
- chip->write_word = ns_nand_write_word;
chip->read_word = ns_nand_read_word;
- chip->eccmode = NAND_ECC_SOFT;
+ chip->ecc.mode = NAND_ECC_SOFT;
chip->options |= NAND_SKIP_BBTSCAN;
/*
chip->options |= NAND_BUSWIDTH_16;
}
+ nsmtd->owner = THIS_MODULE;
+
if ((retval = nand_scan(nsmtd, 1)) != 0) {
NS_ERR("can't register NAND Simulator\n");
if (retval > 0)