#include <linux/init.h>
#include <linux/slab.h>
#include <linux/rslib.h>
+#include <linux/bitrev.h>
#include <linux/module.h>
#include <linux/mtd/compatmac.h>
#include <linux/mtd/mtd.h>
/*
* hardware specific Out Of Band information
*/
-static struct nand_oobinfo rtc_from4_nand_oobinfo = {
- .useecc = MTD_NANDECC_AUTOPLACE,
+static struct nand_ecclayout rtc_from4_nand_oobinfo = {
.eccbytes = 32,
.eccpos = {
0, 1, 2, 3, 4, 5, 6, 7,
.oobfree = {{32, 32}}
};
-/* Aargh. I missed the reversed bit order, when I
- * was talking to Renesas about the FPGA.
- *
- * The table is used for bit reordering and inversion
- * of the ecc byte which we get from the FPGA
- */
-static uint8_t revbits[256] = {
- 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
- 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
- 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
- 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
- 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
- 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
- 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
- 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
- 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
- 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
- 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
- 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
- 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
- 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
- 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
- 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
- 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
- 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
- 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
- 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
- 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
- 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
- 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
- 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
- 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
- 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
- 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
- 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
- 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
- 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
- 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
- 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
-};
-
#endif
/*
* Address lines (A24-A22), so no action is required here.
*
*/
-static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd)
+static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
{
- struct nand_chip *this = (struct nand_chip *)(mtd->priv);
-
- switch (cmd) {
-
- case NAND_CTL_SETCLE:
- this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_CLE);
- break;
- case NAND_CTL_CLRCLE:
- this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_CLE);
- break;
-
- case NAND_CTL_SETALE:
- this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_ALE);
- break;
- case NAND_CTL_CLRALE:
- this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_ALE);
- break;
+ struct nand_chip *chip = (mtd->priv);
- case NAND_CTL_SETNCE:
- break;
- case NAND_CTL_CLRNCE:
- break;
+ if (cmd == NAND_CMD_NONE)
+ return;
- }
+ if (ctrl & NAND_CLE)
+ writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);
+ else
+ writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);
}
/*
/* Read the syndrom pattern from the FPGA and correct the bitorder */
rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
for (i = 0; i < 8; i++) {
- ecc[i] = revbits[(*rs_ecc) & 0xFF];
+ ecc[i] = bitrev8(*rs_ecc);
rs_ecc++;
}
* note: see pages 34..37 of data sheet for details.
*
*/
-static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page)
+static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this,
+ int state, int status, int page)
{
int er_stat = 0;
int rtn, retlen;
this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
if (state == FL_ERASING) {
+
for (i = 0; i < 4; i++) {
- if (status & 1 << (i + 1)) {
- this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1), -1, -1);
- rtn = this->read_byte(mtd);
- this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
- if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
- er_stat |= 1 << (i + 1); /* err_ecc_not_avail */
- }
- }
+ if (!(status & 1 << (i + 1)))
+ continue;
+ this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1),
+ -1, -1);
+ rtn = this->read_byte(mtd);
+ this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
+
+ /* err_ecc_not_avail */
+ if (!(rtn & ERR_STAT_ECC_AVAILABLE))
+ er_stat |= 1 << (i + 1);
}
+
} else if (state == FL_WRITING) {
+
+ unsigned long corrected = mtd->ecc_stats.corrected;
+
/* single bank write logic */
this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1);
rtn = this->read_byte(mtd);
this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
+
if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
- er_stat |= 1 << 1; /* err_ecc_not_avail */
- } else {
- len = mtd->oobblock;
- buf = kmalloc(len, GFP_KERNEL);
- if (!buf) {
- printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
- er_stat = 1; /* if we can't check, assume failed */
- } else {
- /* recovery read */
- /* page read */
- rtn = nand_do_read_ecc(mtd, page, len, &retlen, buf, NULL, this->autooob, 1);
- if (rtn) { /* if read failed or > 1-bit error corrected */
- er_stat |= 1 << 1; /* ECC read failed */
- }
- kfree(buf);
- }
+ /* err_ecc_not_avail */
+ er_stat |= 1 << 1;
+ goto out;
+ }
+
+ len = mtd->writesize;
+ buf = kmalloc(len, GFP_KERNEL);
+ if (!buf) {
+ printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
+ er_stat = 1;
+ goto out;
}
+
+ /* recovery read */
+ rtn = nand_do_read(mtd, page, len, &retlen, buf);
+
+ /* if read failed or > 1-bit error corrected */
+ if (rtn || (mtd->ecc_stats.corrected - corrected) > 1)
+ er_stat |= 1 << 1;
+ kfree(buf);
}
rtn = status;
/*
* Main initialization routine
*/
-int __init rtc_from4_init(void)
+static int __init rtc_from4_init(void)
{
struct nand_chip *this;
unsigned short bcr1, bcr2, wcr2;
/* Link the private data with the MTD structure */
rtc_from4_mtd->priv = this;
+ rtc_from4_mtd->owner = THIS_MODULE;
/* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
bcr1 = *SH77X9_BCR1 & ~0x0002;
this->IO_ADDR_R = rtc_from4_fio_base;
this->IO_ADDR_W = rtc_from4_fio_base;
/* Set address of hardware control function */
- this->hwcontrol = rtc_from4_hwcontrol;
+ this->cmd_ctrl = rtc_from4_hwcontrol;
/* Set address of chip select function */
this->select_chip = rtc_from4_nand_select_chip;
/* command delay time (in us) */
#ifdef RTC_FROM4_HWECC
printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
- this->eccmode = NAND_ECC_HW8_512;
- this->options |= NAND_HWECC_SYNDROME;
+ this->ecc.mode = NAND_ECC_HW_SYNDROME;
+ this->ecc.size = 512;
+ this->ecc.bytes = 8;
/* return the status of extra status and ECC checks */
this->errstat = rtc_from4_errstat;
/* set the nand_oobinfo to support FPGA H/W error detection */
- this->autooob = &rtc_from4_nand_oobinfo;
- this->enable_hwecc = rtc_from4_enable_hwecc;
- this->calculate_ecc = rtc_from4_calculate_ecc;
- this->correct_data = rtc_from4_correct_data;
+ this->ecc.layout = &rtc_from4_nand_oobinfo;
+ this->ecc.hwctl = rtc_from4_enable_hwecc;
+ this->ecc.calculate = rtc_from4_calculate_ecc;
+ this->ecc.correct = rtc_from4_correct_data;
#else
printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
#endif
/* set the bad block tables to support debugging */
/*
* Clean up routine
*/
-#ifdef MODULE
static void __exit rtc_from4_cleanup(void)
{
/* Release resource, unregister partitions */
}
module_exit(rtc_from4_cleanup);
-#endif
MODULE_LICENSE("GPL");
MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
projects / powerpc.git / blobdiff