break;
}
}
+#else
+#define set_msi_affinity NULL
#endif /* CONFIG_SMP */
static void mask_MSI_irq(unsigned int vector)
.disable = mask_MSI_irq,
.ack = mask_MSI_irq,
.end = end_msi_irq_w_maskbit,
- .set_affinity = set_msi_irq_affinity
+ .set_affinity = set_msi_affinity
};
/*
.disable = mask_MSI_irq,
.ack = mask_MSI_irq,
.end = end_msi_irq_w_maskbit,
- .set_affinity = set_msi_irq_affinity
+ .set_affinity = set_msi_affinity
};
/*
.disable = do_nothing,
.ack = do_nothing,
.end = end_msi_irq_wo_maskbit,
- .set_affinity = set_msi_irq_affinity
+ .set_affinity = set_msi_affinity
};
static void msi_data_init(struct msg_data *msi_data,
static void irq_handler_init(int cap_id, int pos, int mask)
{
- spin_lock(&irq_desc[pos].lock);
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq_desc[pos].lock, flags);
if (cap_id == PCI_CAP_ID_MSIX)
irq_desc[pos].handler = &msix_irq_type;
else {
else
irq_desc[pos].handler = &msi_irq_w_maskbit_type;
}
- spin_unlock(&irq_desc[pos].lock);
+ spin_unlock_irqrestore(&irq_desc[pos].lock, flags);
}
static void enable_msi_mode(struct pci_dev *dev, int pos, int type)