Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart

[powerpc.git] / include / asm-ia64 / pal.h

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 20a8d61..4283ddc 100644 (file)
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -78,6 +78,7 @@
 #define PAL_VM_TR_READ         261     /* read contents of translation register */
 #define PAL_GET_PSTATE         262     /* get the current P-state */
 #define PAL_SET_PSTATE         263     /* set the P-state */
+#define PAL_BRAND_INFO         274     /* Processor branding information */
 
 #ifndef __ASSEMBLY__
 
@@ -763,7 +764,7 @@ struct ia64_pal_retval {
  * (generally 0) MUST be passed.  Reserved parameters are not optional
  * parameters.
  */
-extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
+extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
@@ -773,14 +774,7 @@ extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                        \
        struct ia64_fpreg fr[6];                        \
        ia64_save_scratch_fpregs(fr);                   \
-       iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
-       ia64_load_scratch_fpregs(fr);                   \
-} while (0)
-
-#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {         \
-       struct ia64_fpreg fr[6];                        \
-       ia64_save_scratch_fpregs(fr);                   \
-       iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
+       iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
        ia64_load_scratch_fpregs(fr);                   \
 } while (0)
 
@@ -963,7 +957,8 @@ static inline s64
 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 {
        struct ia64_pal_retval iprv;
-       PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
+       PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
+                               physical_addr, 0);
        return iprv.status;
 }
 
@@ -985,7 +980,8 @@ static inline s64
 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 {
        struct ia64_pal_retval iprv;
-       PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
+       PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
+                               physical_addr, data);
        return iprv.status;
 }
 
@@ -1133,6 +1129,15 @@ ia64_pal_set_pstate (u64 pstate_index)
        return iprv.status;
 }
 
+/* Processor branding information*/
+static inline s64
+ia64_pal_get_brand_info (char *brand_info)
+{
+       struct ia64_pal_retval iprv;
+       PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
+       return iprv.status;
+}
+
 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
  * suspended, but cache and TLB coherency is maintained.
  */