[PATCH] FRV: Implement futex operations for FRV

[powerpc.git] / include / asm-mips / mipsregs.h

diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 2a56929..80370e0 100644 (file)
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -95,6 +95,16 @@
 #define CP0_S1_DERRADDR1  $27
 #define CP0_S1_INTCONTROL $20
 
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL    $12   /* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP    $12   /* MIPSR2 */
+
 /*
  *  TX39 Series
  */
@@ -516,6 +526,7 @@
 
 #define MIPS_CONF3_TL          (_ULCAST_(1) <<  0)
 #define MIPS_CONF3_SM          (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT          (_ULCAST_(1) <<  2)
 #define MIPS_CONF3_SP          (_ULCAST_(1) <<  4)
 #define MIPS_CONF3_VINT                (_ULCAST_(1) <<  5)
 #define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
@@ -680,13 +691,13 @@ do {                                                                      \
        if (sel == 0)                                                   \
                __asm__ __volatile__(                                   \
                        "mtc0\t%z0, " #register "\n\t"                  \
-                       : : "Jr" ((unsigned int)value));                \
+                       : : "Jr" ((unsigned int)(value)));              \
        else                                                            \
                __asm__ __volatile__(                                   \
                        ".set\tmips32\n\t"                              \
                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
                        ".set\tmips0"                                   \
-                       : : "Jr" ((unsigned int)value));                \
+                       : : "Jr" ((unsigned int)(value)));              \
 } while (0)
 
 #define __write_64bit_c0_register(register, sel, value)                        \
@@ -735,7 +746,7 @@ do {                                                                        \
 do {                                                                   \
        __asm__ __volatile__(                                           \
                "ctc0\t%z0, " #register "\n\t"                          \
-               : : "Jr" ((unsigned int)value));                        \
+               : : "Jr" ((unsigned int)(value)));                      \
 } while (0)
 
 /*
@@ -828,12 +839,24 @@ do {                                                                      \
 #define read_c0_count()                __read_32bit_c0_register($9, 0)
 #define write_c0_count(val)    __write_32bit_c0_register($9, 0, val)
 
+#define read_c0_count2()       __read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)   __write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3()       __read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)   __write_32bit_c0_register($9, 7, val)
+
 #define read_c0_entryhi()      __read_ulong_c0_register($10, 0)
 #define write_c0_entryhi(val)  __write_ulong_c0_register($10, 0, val)
 
 #define read_c0_compare()      __read_32bit_c0_register($11, 0)
 #define write_c0_compare(val)  __write_32bit_c0_register($11, 0, val)
 
+#define read_c0_compare2()     __read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3()     __read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
+
 #define read_c0_status()       __read_32bit_c0_register($12, 0)
 #define write_c0_status(val)   __write_32bit_c0_register($12, 0, val)
 
@@ -984,6 +1007,22 @@ do {                                                                      \
 #define read_c0_errorepc()     __read_ulong_c0_register($30, 0)
 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
 
+/* MIPSR2 */
+#define read_c0_hwrena()       __read_32bit_c0_register($7,0)
+#define write_c0_hwrena(val)   __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()       __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)   __write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()       __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)   __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()       __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)   __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()                __read_32bit_c0_register($15,1)
+#define write_c0_ebase(val)    __write_32bit_c0_register($15, 1, val)
+
 /*
  * Macros to access the floating point coprocessor control registers
  */
@@ -1357,6 +1396,8 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
 
 #endif /* !__ASSEMBLY__ */