[ARM] 3083/1: include/asm-arm/arch-ixp4xx/io.h: eliminate warnings for pointer passed...

[powerpc.git] / include / asm-powerpc / ppc_asm.h

diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index 6aae414..f99f2af 100644 (file)
--- a/include/asm-powerpc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -76,13 +76,13 @@
 #define REST_16EVRS(n,s,base)  REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
 #define REST_32EVRS(n,s,base)  REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
 
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_VERY_LOW    or   31,31,31  # very low priority\n"
-#define HMT_LOW                or 1,1,1
-#define HMT_MEDIUM_LOW  or   6,6,6     # medium low priority\n"
-#define HMT_MEDIUM     or 2,2,2
-#define HMT_MEDIUM_HIGH or   5,5,5     # medium high priority\n"
-#define HMT_HIGH       or 3,3,3
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW   or      31,31,31        # very low priority
+#define HMT_LOW                or      1,1,1
+#define HMT_MEDIUM_LOW  or     6,6,6           # medium low priority
+#define HMT_MEDIUM     or      2,2,2
+#define HMT_MEDIUM_HIGH or     5,5,5           # medium high priority
+#define HMT_HIGH       or      3,3,3
 
 /* handle instructions that older assemblers may not know */
 #define RFCI           .long 0x4c000066        /* rfci instruction */
@@ -154,7 +154,7 @@ n:
  *   loads the address of 'name' into 'rn'
  *
  * LOADBASE( rn, name )
- *   loads the address (less the low 16 bits) of 'name' into 'rn'
+ *   loads the address (possibly without the low 16 bits) of 'name' into 'rn'
  *   suitable for base+disp addressing
  */
 #ifdef __powerpc64__
@@ -166,10 +166,7 @@ n:
        ori     rn,rn,name##@l
 
 #define LOADBASE(rn,name)              \
-       .section .toc,"aw";             \
-1:     .tc     name[TC],name;          \
-       .previous;                      \
-       ld      rn,1b@toc(r2)
+       ld      rn,name@got(r2)
 
 #define OFF(name)      0
 
@@ -191,10 +188,14 @@ n:
 #define LDL    ld
 #define STL    std
 #define CMPI   cmpdi
+#define SZL    8
+
+/* offsets for stack frame layout */
+#define LRSAVE 16
 
 #else /* 32-bit */
 #define LOADADDR(rn,name) \
-       lis     rn,name@ha      \
+       lis     rn,name@ha;     \
        addi    rn,rn,name@l
 
 #define LOADBASE(rn,name)      \
@@ -206,6 +207,10 @@ n:
 #define LDL    lwz
 #define STL    stw
 #define CMPI   cmpwi
+#define SZL    4
+
+/* offsets for stack frame layout */
+#define LRSAVE 4
 
 #endif
 
@@ -278,6 +283,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 
 
 #if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
+
 #define tophys(rd,rs)                          \
        addis   rd,rs,0
 
@@ -285,23 +293,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
        addis   rd,rs,0
 
 #elif defined(CONFIG_PPC64)
-/* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
+#define toreal(rd)             /* we can access c000... in real mode */
+#define fromreal(rd)
+
 #define tophys(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        sub     rd,rs,rd
+       clrldi  rd,rs,2
 
 #define tovirt(rd,rs)                           \
-        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
-        rldicr  rd,rd,32,31;                    \
-        add     rd,rs,rd
+       rotldi  rd,rs,16;                       \
+       ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
+       rotldi  rd,rd,48
 #else
 /*
  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
  * physical base address of RAM at compile time.
  */
+#define toreal(rd)     tophys(rd,rd)
+#define fromreal(rd)   tovirt(rd,rd)
+
 #define tophys(rd,rs)                          \
 0:     addis   rd,rs,-KERNELBASE@h;            \
        .section ".vtop_fixup","aw";            \