[POWERPC] Cell timebase bug workaround
[powerpc.git] / include / asm-powerpc / reg.h
index fde5c80..6faae7b 100644 (file)
                                : "=r" (rval)); rval;})
 #define mtspr(rn, v)   asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
 
+#ifdef __powerpc64__
+#ifdef CONFIG_PPC_CELL
+#define mftb()         ({unsigned long rval;                           \
+                       asm volatile(                                   \
+                               "90:    mftb %0;\n"                     \
+                               "97:    cmpwi %0,0;\n"                  \
+                               "       beq- 90b;\n"                    \
+                               "99:\n"                                 \
+                               ".section __ftr_fixup,\"a\"\n"          \
+                               ".align 3\n"                            \
+                               "98:\n"                                 \
+                               "       .llong %1\n"                    \
+                               "       .llong %1\n"                    \
+                               "       .llong 97b-98b\n"               \
+                               "       .llong 99b-98b\n"               \
+                               ".previous"                             \
+                       : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
+#else
 #define mftb()         ({unsigned long rval;   \
                        asm volatile("mftb %0" : "=r" (rval)); rval;})
+#endif /* !CONFIG_PPC_CELL */
+
+#else /* __powerpc64__ */
+
 #define mftbl()                ({unsigned long rval;   \
                        asm volatile("mftbl %0" : "=r" (rval)); rval;})
+#define mftbu()                ({unsigned long rval;   \
+                       asm volatile("mftbu %0" : "=r" (rval)); rval;})
+#endif /* !__powerpc64__ */
 
 #define mttbl(v)       asm volatile("mttbl %0":: "r"(v))
 #define mttbu(v)       asm volatile("mttbu %0":: "r"(v))