[POWERPC] Fix MMIO ops to provide expected barrier behaviour

[powerpc.git] / include / asm-powerpc / tlbflush.h

diff --git a/include/asm-powerpc/tlbflush.h b/include/asm-powerpc/tlbflush.h
index ca36556..93c7d0c 100644 (file)
--- a/include/asm-powerpc/tlbflush.h
+++ b/include/asm-powerpc/tlbflush.h
@@ -17,7 +17,6 @@
  */
 #ifdef __KERNEL__
 
-#include <linux/config.h>
 
 struct mm_struct;
 
@@ -31,9 +30,9 @@ struct mm_struct;
 struct ppc64_tlb_batch {
        unsigned long index;
        struct mm_struct *mm;
-       pte_t pte[PPC64_TLB_BATCH_NR];
+       real_pte_t pte[PPC64_TLB_BATCH_NR];
        unsigned long vaddr[PPC64_TLB_BATCH_NR];
-       unsigned int large;
+       unsigned int psize;
 };
 DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 
@@ -48,8 +47,9 @@ static inline void flush_tlb_pending(void)
        put_cpu_var(ppc64_tlb_batch);
 }
 
-extern void flush_hash_page(unsigned long va, pte_t pte, int local);
-void flush_hash_range(unsigned long number, int local);
+extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
+                           int local);
+extern void flush_hash_range(unsigned long number, int local);
 
 #else /* CONFIG_PPC64 */