Merge branch 'intelfb-patches' of master.kernel.org:/pub/scm/linux/kernel/git/airlied...

[powerpc.git] / include / asm-ppc / reg_booke.h

diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 4b03f8e..602fbad 100644 (file)
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -165,6 +165,8 @@ do {                                                \
 #define SPRN_MCSRR1    0x23B   /* Machine Check Save and Restore Register 1 */
 #define SPRN_MCSR      0x23C   /* Machine Check Status Register */
 #define SPRN_MCAR      0x23D   /* Machine Check Address Register */
+#define SPRN_DSRR0     0x23E   /* Debug Save and Restore Register 0 */
+#define SPRN_DSRR1     0x23F   /* Debug Save and Restore Register 1 */
 #define SPRN_MAS0      0x270   /* MMU Assist Register 0 */
 #define SPRN_MAS1      0x271   /* MMU Assist Register 1 */
 #define SPRN_MAS2      0x272   /* MMU Assist Register 2 */
@@ -172,6 +174,7 @@ do {                                                \
 #define SPRN_MAS4      0x274   /* MMU Assist Register 4 */
 #define SPRN_MAS5      0x275   /* MMU Assist Register 5 */
 #define SPRN_MAS6      0x276   /* MMU Assist Register 6 */
+#define SPRN_MAS7      0x3b0   /* MMU Assist Register 7 */
 #define SPRN_PID1      0x279   /* Process ID Register 1 */
 #define SPRN_PID2      0x27A   /* Process ID Register 2 */
 #define SPRN_TLB0CFG   0x2B0   /* TLB 0 Config Register */
@@ -234,6 +237,7 @@ do {                                                \
 #endif
 
 /* Bit definitions for CCR1. */
+#define        CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define        CCR1_TCS        0x00000080 /* Timer Clock Select */
 
 /* Bit definitions for the MCSR. */
@@ -263,6 +267,17 @@ do {                                               \
 #define MCSR_BUS_IPERR         0x00000002UL /* Instruction parity Error */
 #define MCSR_BUS_RPERR         0x00000001UL /* Read parity Error */
 #endif
+#ifdef CONFIG_E200
+#define MCSR_MCP       0x80000000UL /* Machine Check Input Pin */
+#define MCSR_CP_PERR   0x20000000UL /* Cache Push Parity Error */
+#define MCSR_CPERR     0x10000000UL /* Cache Parity Error */
+#define MCSR_EXCP_ERR  0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
+                                       fetch for an exception handler */
+#define MCSR_BUS_IRERR         0x00000010UL /* Read Bus Error on instruction fetch*/
+#define MCSR_BUS_DRERR         0x00000008UL /* Read Bus Error on data load */
+#define MCSR_BUS_WRERR         0x00000004UL /* Write Bus Error on buffered
+                                       store or cache line push */
+#endif
 
 /* Bit definitions for the DBSR. */
 /*
@@ -285,14 +300,14 @@ do {                                              \
 #define DBSR_IC                0x80000000      /* Instruction Completion */
 #define DBSR_BT                0x40000000      /* Branch taken */
 #define DBSR_TIE       0x10000000      /* Trap Instruction debug Event */
-#define DBSR_IAC1      0x00800000      /* Instruction Address Compare 1 Event */
-#define DBSR_IAC2      0x00400000      /* Instruction Address Compare 2 Event */
-#define DBSR_IAC3      0x00200000      /* Instruction Address Compare 3 Event */
-#define DBSR_IAC4      0x00100000      /* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R     0x00080000      /* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W     0x00040000      /* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R     0x00020000      /* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W     0x00010000      /* Data Address Compare 2 Write Event */
+#define DBSR_IAC1      0x04000000      /* Instruction Address Compare 1 Event */
+#define DBSR_IAC2      0x02000000      /* Instruction Address Compare 2 Event */
+#define DBSR_IAC3      0x00080000      /* Instruction Address Compare 3 Event */
+#define DBSR_IAC4      0x00040000      /* Instruction Address Compare 4 Event */
+#define DBSR_DAC1R     0x01000000      /* Data Address Compare 1 Read Event */
+#define DBSR_DAC1W     0x00800000      /* Data Address Compare 1 Write Event */
+#define DBSR_DAC2R     0x00400000      /* Data Address Compare 2 Read Event */
+#define DBSR_DAC2W     0x00200000      /* Data Address Compare 2 Write Event */
 #endif
 
 /* Bit definitions related to the ESR. */
@@ -304,11 +319,13 @@ do {                                              \
 #define ESR_PIL                0x08000000      /* Program Exception - Illegal */
 #define ESR_PPR                0x04000000      /* Program Exception - Priveleged */
 #define ESR_PTR                0x02000000      /* Program Exception - Trap */
+#define ESR_FP         0x01000000      /* Floating Point Operation */
 #define ESR_DST                0x00800000      /* Storage Exception - Data miss */
 #define ESR_DIZ                0x00400000      /* Storage Exception - Zone fault */
 #define ESR_ST         0x00800000      /* Store Operation */
 #define ESR_DLK                0x00200000      /* Data Cache Locking */
 #define ESR_ILK                0x00100000      /* Instr. Cache Locking */
+#define ESR_PUO                0x00040000      /* Unimplemented Operation exception */
 #define ESR_BO         0x00020000      /* Byte Ordering */
 
 /* Bit definitions related to the DBCR0. */
@@ -385,10 +402,12 @@ do {                                              \
 #define ICCR_CACHE     1               /* Cacheable */
 
 /* Bit definitions for L1CSR0. */
+#define L1CSR0_CLFC    0x00000100      /* Cache Lock Bits Flash Clear */
 #define L1CSR0_DCFI    0x00000002      /* Data Cache Flash Invalidate */
+#define L1CSR0_CFI     0x00000002      /* Cache Flash Invalidate */
 #define L1CSR0_DCE     0x00000001      /* Data Cache Enable */
 
-/* Bit definitions for L1CSR0. */
+/* Bit definitions for L1CSR1. */
 #define L1CSR1_ICLFR   0x00000100      /* Instr Cache Lock Bits Flash Reset */
 #define L1CSR1_ICFI    0x00000002      /* Instr Cache Flash Invalidate */
 #define L1CSR1_ICE     0x00000001      /* Instr Cache Enable */