/*
* This is a template for all of the 128 devices, hopefuly
*/
-struct mcu_t {
+const struct mcu_t {
avr_t core;
avr_eeprom_t eeprom;
avr_flash_t selfprog;
.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+ .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+ .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
.r_ucsra = UCSR0A,
.r_ucsrb = UCSR0B,
.txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
.rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+ .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+ .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
.r_ucsra = UCSR1A,
.r_ucsrb = UCSR1B,
AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
AVR_IO_REGBIT(ADMUX, MUX4),},
.ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+ .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256 },
+
.adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
.r_adcsra = ADCSRA,
.aden = AVR_IO_REGBIT(ADCSRA, ADEN),
//.r_adcsrb = ADCSRB,
// .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+ .muxmode = {
+ [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+ [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+ [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
+ [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
+
+ [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
+ [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
+ [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
+ [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
+
+ [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
+ [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
+ [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
+ [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
+
+ [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
+ [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
+ [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
+
+ [30] = AVR_ADC_REF(1230), // 1.1V
+ [31] = AVR_ADC_REF(0), // GND
+ },
+
.adc = {
.enable = AVR_IO_REGBIT(ADCSRA, ADIE),
.raised = AVR_IO_REGBIT(ADCSRA, ADIF),
// asynchronous timer source bit.. if set, use 32khz frequency
.as2 = AVR_IO_REGBIT(ASSR, AS0),
- .r_ocra = OCR0,
.r_tcnt = TCNT0,
.overflow = {
.raised = AVR_IO_REGBIT(TIFR, TOV0),
.vector = TIMER0_OVF_vect,
},
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE0),
- .raised = AVR_IO_REGBIT(TIFR, OCF0),
- .vector = TIMER0_COMP_vect,
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR0,
+ .com = AVR_IO_REGBITS(TCCR0, COM00, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, PB4),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE0),
+ .raised = AVR_IO_REGBIT(TIFR, OCF0),
+ .vector = TIMER0_COMP_vect,
+ },
+ },
},
},
.timer1 = {
AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
.wgm_op = {
[0] = AVR_TIMER_WGM_NORMAL16(),
- // TODO: 1 PWM phase corret 8bit
- // 2 PWM phase corret 9bit
- // 3 PWM phase corret 10bit
+ // TODO: 1 PWM phase correct 8bit
+ // 2 PWM phase correct 9bit
+ // 3 PWM phase correct 10bit
[4] = AVR_TIMER_WGM_CTC(),
[5] = AVR_TIMER_WGM_FASTPWM8(),
[6] = AVR_TIMER_WGM_FASTPWM9(),
.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
- .r_ocra = OCR1AL,
- .r_ocrb = OCR1BL,
- .r_ocrc = OCR1CL,
.r_tcnt = TCNT1L,
.r_icr = ICR1L,
.r_icrh = ICR1H,
- .r_ocrah = OCR1AH, // 16 bits timers have two bytes of it
- .r_ocrbh = OCR1BH,
- .r_ocrch = OCR1CH,
.r_tcnth = TCNT1H,
+ .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
+ .icp = AVR_IO_REGBIT(PORTD, 4),
+
.overflow = {
.enable = AVR_IO_REGBIT(TIMSK, TOIE1),
.raised = AVR_IO_REGBIT(TIFR, TOV1),
.vector = TIMER1_OVF_vect,
},
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
- .raised = AVR_IO_REGBIT(TIFR, OCF1A),
- .vector = TIMER1_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
- .raised = AVR_IO_REGBIT(TIFR, OCF1B),
- .vector = TIMER1_COMPB_vect,
- },
- .compc = {
- .enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
- .raised = AVR_IO_REGBIT(ETIFR, OCF1C),
- .vector = TIMER1_COMPC_vect,
- },
.icr = {
.enable = AVR_IO_REGBIT(TIMSK, TICIE1),
.raised = AVR_IO_REGBIT(TIFR, ICF1),
.vector = TIMER1_CAPT_vect,
},
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR1AL,
+ .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
+ .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, PB5),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+ .raised = AVR_IO_REGBIT(TIFR, OCF1A),
+ .vector = TIMER1_COMPA_vect,
+ },
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR1BL,
+ .r_ocrh = OCR1BH,
+ .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, PB6),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+ .raised = AVR_IO_REGBIT(TIFR, OCF1B),
+ .vector = TIMER1_COMPB_vect,
+ },
+ },
+ [AVR_TIMER_COMPC] = {
+ .r_ocr = OCR1CL,
+ .r_ocrh = OCR1CH,
+ .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer2
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
+ .raised = AVR_IO_REGBIT(ETIFR, OCF1C),
+ .vector = TIMER1_COMPC_vect,
+ },
+ },
+ },
+
},
.timer2 = {
.name = '2',
.cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) },
.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
- .r_ocra = OCR2,
.r_tcnt = TCNT2,
.overflow = {
.raised = AVR_IO_REGBIT(TIFR, TOV2),
.vector = TIMER2_OVF_vect,
},
- .compa = { // compa is just COMP
- .enable = AVR_IO_REGBIT(TIMSK, OCIE2),
- .raised = AVR_IO_REGBIT(TIFR, OCF2),
- .vector = TIMER2_COMP_vect,
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR2,
+ .com = AVR_IO_REGBITS(TCCR2, COM20, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE2),
+ .raised = AVR_IO_REGBIT(TIFR, OCF2),
+ .vector = TIMER2_COMP_vect,
+ },
+ },
},
},
.timer3 = {
AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
.wgm_op = {
[0] = AVR_TIMER_WGM_NORMAL16(),
- // TODO: 1 PWM phase corret 8bit
- // 2 PWM phase corret 9bit
- // 3 PWM phase corret 10bit
+ // TODO: 1 PWM phase correct 8bit
+ // 2 PWM phase correct 9bit
+ // 3 PWM phase correct 10bit
[4] = AVR_TIMER_WGM_CTC(),
[5] = AVR_TIMER_WGM_FASTPWM8(),
[6] = AVR_TIMER_WGM_FASTPWM9(),
[7] = AVR_TIMER_WGM_FASTPWM10(),
- // TODO: 8 PWM phase and freq corret ICR
- // 9 PWM phase and freq corret OCR
+ // TODO: 8 PWM phase and freq correct ICR
+ // 9 PWM phase and freq correct OCR
// 10
// 11
[12] = AVR_TIMER_WGM_ICCTC(),
.cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
- .r_ocra = OCR3AL,
- .r_ocrb = OCR3BL,
- .r_ocrc = OCR3CL,
.r_tcnt = TCNT3L,
.r_icr = ICR3L,
.r_icrh = ICR3H,
- .r_ocrah = OCR3AH, // 16 bits timers have two bytes of it
- .r_ocrbh = OCR3BH,
- .r_ocrch = OCR3CH,
.r_tcnth = TCNT3H,
+ .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
+ .icp = AVR_IO_REGBIT(PORTE, 7),
+
.overflow = {
.enable = AVR_IO_REGBIT(ETIMSK, TOIE3),
.raised = AVR_IO_REGBIT(ETIFR, TOV3),
.vector = TIMER3_OVF_vect,
},
- .compa = {
- .enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
- .raised = AVR_IO_REGBIT(ETIFR, OCF3A),
- .vector = TIMER3_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
- .raised = AVR_IO_REGBIT(ETIFR, OCF3B),
- .vector = TIMER3_COMPB_vect,
- },
- .compc = {
- .enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
- .raised = AVR_IO_REGBIT(ETIFR, OCF3C),
- .vector = TIMER3_COMPC_vect,
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR3AL,
+ .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
+ .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTE, PE3),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
+ .raised = AVR_IO_REGBIT(ETIFR, OCF3A),
+ .vector = TIMER3_COMPA_vect,
+ }
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR3BL,
+ .r_ocrh = OCR3BH,
+ .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTE, PE4),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
+ .raised = AVR_IO_REGBIT(ETIFR, OCF3B),
+ .vector = TIMER3_COMPB_vect,
+ }
+ },
+ [AVR_TIMER_COMPC] = {
+ .r_ocr = OCR3CL,
+ .r_ocrh = OCR3CH,
+ .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTE, PE5),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
+ .raised = AVR_IO_REGBIT(ETIFR, OCF3C),
+ .vector = TIMER3_COMPC_vect,
+ }
+ }
},
.icr = {
.enable = AVR_IO_REGBIT(ETIMSK, TICIE3),
.twi = {
.enable = AVR_IO_REGBIT(TWCR, TWIE),
- .raised = AVR_IO_REGBIT(TWSR, TWINT),
+ .raised = AVR_IO_REGBIT(TWCR, TWINT),
.vector = TWI_vect,
},
},
static avr_t * make()
{
- return &mcu_mega128.core;
+ return avr_core_allocate(&mcu_mega128.core, sizeof(struct mcu_t));
}
avr_kind_t mega128 = {
projects / simavr / blobdiff