cores: Now duplicate the global structure

[simavr] / simavr / cores / sim_tinyx5.h

diff --git a/simavr/cores/sim_tinyx5.h b/simavr/cores/sim_tinyx5.h
index 9dda7ed..44dbd06 100644 (file)
--- a/simavr/cores/sim_tinyx5.h
+++ b/simavr/cores/sim_tinyx5.h
@@ -26,6 +26,7 @@
 
 #include "sim_core_declare.h"
 #include "avr_eeprom.h"
+#include "avr_watchdog.h"
 #include "avr_extint.h"
 #include "avr_ioport.h"
 #include "avr_adc.h"
@@ -40,6 +41,7 @@ void tx5_reset(struct avr_t * avr);
 struct mcu_t {
        avr_t core;
        avr_eeprom_t    eeprom;
+       avr_watchdog_t  watchdog;
        avr_extint_t    extint;
        avr_ioport_t    portb;
        avr_adc_t               adc;
@@ -55,7 +57,7 @@ struct mcu_t {
 #error SIM_MMCU is not declared
 #endif
 
-struct mcu_t SIM_CORENAME = {
+const struct mcu_t SIM_CORENAME = {
        .core = {
                .mmcu = SIM_MMCU,
                DEFAULT_CORE(SIM_VECTOR_SIZE),
@@ -64,6 +66,7 @@ struct mcu_t SIM_CORENAME = {
                .reset = tx5_reset,
        },
        AVR_EEPROM_DECLARE(EE_RDY_vect),
+       AVR_WATCHDOG_DECLARE(WDTCR, WDT_vect),
        .extint = {
                AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
        },
@@ -81,6 +84,12 @@ struct mcu_t SIM_CORENAME = {
                .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
                                        AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
                .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), AVR_IO_REGBIT(ADMUX, REFS2), },
+               .ref_values = {
+                               [0] = ADC_VREF_VCC, [1] = ADC_VREF_AVCC,
+                               [2] = ADC_VREF_V110, [5] = ADC_VREF_V256,
+                               [6] = ADC_VREF_V256,
+               },
+
                .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
                .r_adcsra = ADCSRA,
                .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
@@ -96,6 +105,19 @@ struct mcu_t SIM_CORENAME = {
                .bin = AVR_IO_REGBIT(ADCSRB, BIN),
                .ipr = AVR_IO_REGBIT(ADCSRA, IPR),
 
+               .muxmode = {
+                       [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+                       [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+
+                       [ 4] = AVR_ADC_DIFF(2, 2,   1), [ 5] = AVR_ADC_DIFF(2, 2,  20),
+                       [ 6] = AVR_ADC_DIFF(2, 3,   1), [ 7] = AVR_ADC_DIFF(2, 3,  20),
+                       [ 8] = AVR_ADC_DIFF(0, 0,   1), [ 9] = AVR_ADC_DIFF(0, 0,  20),
+                       [10] = AVR_ADC_DIFF(0, 1,   1), [11] = AVR_ADC_DIFF(0, 1,  20),
+                       [12] = AVR_ADC_REF(1100),       // Vbg
+                       [13] = AVR_ADC_REF(0),          // GND
+                       [15] = AVR_ADC_TEMP(),
+               },
+
                .adc = {
                        .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
                        .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
@@ -114,8 +136,6 @@ struct mcu_t SIM_CORENAME = {
                .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-               .r_ocra = OCR0A,
-               .r_ocrb = OCR0B,
                .r_tcnt = TCNT0,
 
                .overflow = {
@@ -123,15 +143,27 @@ struct mcu_t SIM_CORENAME = {
                        .raised = AVR_IO_REGBIT(TIFR, TOV0),
                        .vector = TIMER0_OVF_vect,
                },
-               .compa = {
-                       .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
-                       .raised = AVR_IO_REGBIT(TIFR, OCF0A),
-                       .vector = TIMER0_COMPA_vect,
-               },
-               .compb = {
-                       .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
-                       .raised = AVR_IO_REGBIT(TIFR, OCF0B),
-                       .vector = TIMER0_COMPB_vect,
+               .comp = {
+                       [AVR_TIMER_COMPA] = {
+                               .r_ocr = OCR0A,
+                               .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
+                               .com_pin = AVR_IO_REGBIT(PORTB, 0),
+                               .interrupt = {
+                                       .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
+                                       .raised = AVR_IO_REGBIT(TIFR, OCF0A),
+                                       .vector = TIMER0_COMPA_vect,
+                               },
+                       },
+                       [AVR_TIMER_COMPB] = {
+                               .r_ocr = OCR0B,
+                               .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
+                               .com_pin = AVR_IO_REGBIT(PORTB, 1),
+                               .interrupt = {
+                                       .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
+                                       .raised = AVR_IO_REGBIT(TIFR, OCF0B),
+                                       .vector = TIMER0_COMPB_vect,
+                               },
+                       },
                },
        },
        .timer1 = {
@@ -140,9 +172,6 @@ struct mcu_t SIM_CORENAME = {
                .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) },
                .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ },
 
-               .r_ocra = OCR1A,
-               .r_ocrb = OCR1B,
-               .r_ocrc = OCR1C,
                .r_tcnt = TCNT1,
 
                .overflow = {
@@ -150,19 +179,32 @@ struct mcu_t SIM_CORENAME = {
                        .raised = AVR_IO_REGBIT(TIFR, TOV1),
                        .vector = TIMER1_OVF_vect,
                },
-               .compa = {
-                       .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
-                       .raised = AVR_IO_REGBIT(TIFR, OCF1A),
-                       .vector = TIMER1_COMPA_vect,
-               },
-               .compb = {
-                       .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
-                       .raised = AVR_IO_REGBIT(TIFR, OCF1B),
-                       .vector = TIMER1_COMPB_vect,
+               .comp = {
+                       [AVR_TIMER_COMPA] = {
+                               .r_ocr = OCR1A,
+                               .com = AVR_IO_REGBITS(TCCR1, COM1A0, 0x3),
+                               .com_pin = AVR_IO_REGBIT(PORTB, 1),
+                               .interrupt = {
+                                       .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+                                       .raised = AVR_IO_REGBIT(TIFR, OCF1A),
+                                       .vector = TIMER1_COMPA_vect,
+                               },
+                       },
+                       [AVR_TIMER_COMPB] = {
+                               .r_ocr = OCR1B,
+                               .com = AVR_IO_REGBITS(GTCCR, COM1B0, 0x3),
+                               .com_pin = AVR_IO_REGBIT(PORTB, 4),
+                               .interrupt = {
+                                       .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+                                       .raised = AVR_IO_REGBIT(TIFR, OCF1B),
+                                       .vector = TIMER1_COMPB_vect,
+                               },
+                       },
+                       [AVR_TIMER_COMPC] = {
+                               .r_ocr = OCR1C,
+                       },
                },
        },
-
-
 };
 #endif /* SIM_CORENAME */