#include "sim_core_declare.h"
#include "avr_eeprom.h"
+#include "avr_watchdog.h"
+#include "avr_extint.h"
#include "avr_ioport.h"
-#include "avr_timer8.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
void tx5_init(struct avr_t * avr);
void tx5_reset(struct avr_t * avr);
struct mcu_t {
avr_t core;
avr_eeprom_t eeprom;
+ avr_watchdog_t watchdog;
+ avr_extint_t extint;
avr_ioport_t portb;
- avr_timer8_t timer0, timer1;
+ avr_adc_t adc;
+ avr_timer_t timer0, timer1;
};
#ifdef SIM_CORENAME
#error SIM_MMCU is not declared
#endif
-struct mcu_t SIM_CORENAME = {
+const struct mcu_t SIM_CORENAME = {
.core = {
.mmcu = SIM_MMCU,
DEFAULT_CORE(SIM_VECTOR_SIZE),
.reset = tx5_reset,
},
AVR_EEPROM_DECLARE(EE_RDY_vect),
+ AVR_WATCHDOG_DECLARE(WDTCR, WDT_vect),
+ .extint = {
+ AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
+ },
.portb = {
.name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
.pcint = {
},
.r_pcint = PCMSK,
},
+ .adc = {
+ .r_admux = ADMUX,
+ .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
+ AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
+ .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), AVR_IO_REGBIT(ADMUX, REFS2), },
+ .ref_values = {
+ [0] = ADC_VREF_VCC, [1] = ADC_VREF_AVCC,
+ [2] = ADC_VREF_V110, [5] = ADC_VREF_V256,
+ [6] = ADC_VREF_V256,
+ },
+
+ .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
+ .r_adcsra = ADCSRA,
+ .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
+ .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
+ .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
+ .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
+
+ .r_adch = ADCH,
+ .r_adcl = ADCL,
+
+ .r_adcsrb = ADCSRB,
+ .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+ .bin = AVR_IO_REGBIT(ADCSRB, BIN),
+ .ipr = AVR_IO_REGBIT(ADCSRA, IPR),
+
+ .muxmode = {
+ [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+ [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+
+ [ 4] = AVR_ADC_DIFF(2, 2, 1), [ 5] = AVR_ADC_DIFF(2, 2, 20),
+ [ 6] = AVR_ADC_DIFF(2, 3, 1), [ 7] = AVR_ADC_DIFF(2, 3, 20),
+ [ 8] = AVR_ADC_DIFF(0, 0, 1), [ 9] = AVR_ADC_DIFF(0, 0, 20),
+ [10] = AVR_ADC_DIFF(0, 1, 1), [11] = AVR_ADC_DIFF(0, 1, 20),
+ [12] = AVR_ADC_REF(1100), // Vbg
+ [13] = AVR_ADC_REF(0), // GND
+ [15] = AVR_ADC_TEMP(),
+ },
+
+ .adc = {
+ .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
+ .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
+ .vector = ADC_vect,
+ },
+ },
.timer0 = {
.name = '0',
.wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+ .wgm_op = {
+ [0] = AVR_TIMER_WGM_NORMAL8(),
+ [2] = AVR_TIMER_WGM_CTC(),
+ [3] = AVR_TIMER_WGM_FASTPWM8(),
+ [7] = AVR_TIMER_WGM_OCPWM(),
+ },
.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
- .r_ocra = OCR0A,
- .r_ocrb = OCR0B,
.r_tcnt = TCNT0,
.overflow = {
.raised = AVR_IO_REGBIT(TIFR, TOV0),
.vector = TIMER0_OVF_vect,
},
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
- .raised = AVR_IO_REGBIT(TIFR, OCF0A),
- .vector = TIMER0_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
- .raised = AVR_IO_REGBIT(TIFR, OCF0B),
- .vector = TIMER0_COMPB_vect,
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR0A,
+ .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 0),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
+ .raised = AVR_IO_REGBIT(TIFR, OCF0A),
+ .vector = TIMER0_COMPA_vect,
+ },
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR0B,
+ .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 1),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
+ .raised = AVR_IO_REGBIT(TIFR, OCF0B),
+ .vector = TIMER0_COMPB_vect,
+ },
+ },
},
},
.timer1 = {
.cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) },
.cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ },
- .r_ocra = OCR1A,
- .r_ocrb = OCR1B,
- .r_ocrc = OCR1C,
.r_tcnt = TCNT1,
.overflow = {
.raised = AVR_IO_REGBIT(TIFR, TOV1),
.vector = TIMER1_OVF_vect,
},
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
- .raised = AVR_IO_REGBIT(TIFR, OCF1A),
- .vector = TIMER1_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
- .raised = AVR_IO_REGBIT(TIFR, OCF1B),
- .vector = TIMER1_COMPB_vect,
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR1A,
+ .com = AVR_IO_REGBITS(TCCR1, COM1A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 1),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+ .raised = AVR_IO_REGBIT(TIFR, OCF1A),
+ .vector = TIMER1_COMPA_vect,
+ },
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR1B,
+ .com = AVR_IO_REGBITS(GTCCR, COM1B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 4),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+ .raised = AVR_IO_REGBIT(TIFR, OCF1B),
+ .vector = TIMER1_COMPB_vect,
+ },
+ },
+ [AVR_TIMER_COMPC] = {
+ .r_ocr = OCR1C,
+ },
},
},
-
-
};
#endif /* SIM_CORENAME */
projects / simavr / blobdiff