#include <stdio.h>
#include <unistd.h>
#include <stdint.h>
+#include <stdlib.h>
#include "avr_uart.h"
#include "sim_hex.h"
-DEFINE_FIFO(uint8_t, uart_fifo, 64);
+//#define TRACE(_w) _w
+#ifndef TRACE
+#define TRACE(_w)
+#endif
+
+DEFINE_FIFO(uint8_t, uart_fifo);
static avr_cycle_count_t avr_uart_txc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
{
usleep(1);
}
// if reception is idle and the fifo is empty, tell whomever there is room
- if (avr_regbit_get(avr, p->rxen))
- avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, uart_fifo_isempty(&p->input) != 0);
+ if (avr_regbit_get(avr, p->rxen) && uart_fifo_isempty(&p->input)) {
+ avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 0);
+ avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, 1);
+ }
return v;
}
}
uint8_t v = uart_fifo_read(&p->input);
- //printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");
+// TRACE(printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");)
avr->data[addr] = v;
// made to trigger potential watchpoints
v = avr_core_watch_read(avr, addr);
- // should always trigger that timer
-// if (!uart_fifo_isempty(&p->input))
- avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
+ // trigger timer if more characters are pending
+ if (!uart_fifo_isempty(&p->input))
+ avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
return v;
}
int sb = 1 + avr_regbit_get(avr, p->usbs);
int word_size = 1 /* start */ + db /* data bits */ + 1 /* parity */ + sb /* stops */;
- printf("UART-%c configured to %04x = %d bps, %d data %d stop\n",
- p->name, val, baud, db, sb);
+ printf("UART-%c configured to %04x = %d bps (x%d), %d data %d stop\n",
+ p->name, val, baud, avr_regbit_get(avr, p->u2x)?2:1, db, sb);
// TODO: Use the divider value and calculate the straight number of cycles
p->usec_per_byte = 1000000 / (baud / word_size);
printf("Roughtly %d usec per bytes\n", (int)p->usec_per_byte);
if (addr == p->r_udr) {
avr_core_watch_write(avr, addr, v);
- avr_regbit_clear(avr, p->udrc.raised);
+ if ( p->udrc.vector)
+ avr_regbit_clear(avr, p->udrc.raised);
avr_cycle_timer_register_usec(avr,
p->usec_per_byte, avr_uart_txc_raise, p); // should be uart speed dependent
if (p->flags & AVR_UART_FLAG_STDIO) {
- static char buf[128];
- static int l = 0;
- buf[l++] = v < ' ' ? '.' : v;
- buf[l] = 0;
- if (v == '\n' || l == 127) {
- l = 0;
- printf( FONT_GREEN "%s\n" FONT_DEFAULT, buf);
+ const int maxsize = 256;
+ if (!p->stdio_out)
+ p->stdio_out = malloc(maxsize);
+ p->stdio_out[p->stdio_len++] = v < ' ' ? '.' : v;
+ p->stdio_out[p->stdio_len] = 0;
+ if (v == '\n' || p->stdio_len == maxsize) {
+ p->stdio_len = 0;
+ printf( FONT_GREEN "%s\n" FONT_DEFAULT, p->stdio_out);
}
}
- // printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
+ TRACE(printf("UDR%c(%02x) = %02x\n", p->name, addr, v);)
// tell other modules we are "outputing" a byte
if (avr_regbit_get(avr, p->txen))
avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
}
- if (addr == p->udrc.enable.reg) {
+ if (p->udrc.vector && addr == p->udrc.enable.reg) {
/*
* If enabling the UDRC interrupt, raise it immediately if FIFO is empty
*/
avr_raise_interrupt(avr, &p->udrc);
}
}
- if (addr == p->udrc.raised.reg) {
+ if (p->udrc.vector && addr == p->udrc.raised.reg) {
// get the bits before the write
//uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
uint8_t txc = avr_regbit_get(avr, p->txc.raised);
avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p); // should be uart speed dependent
uart_fifo_write(&p->input, value); // add to fifo
-// printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");
+ TRACE(printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");)
- avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, uart_fifo_isfull(&p->input) != 0);
+ if (uart_fifo_isfull(&p->input))
+ avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 1);
}
{
avr_uart_t * p = (avr_uart_t *)io;
avr_t * avr = p->io.avr;
- avr_regbit_set(avr, p->udrc.raised);
+ if (p->udrc.vector)
+ avr_regbit_set(avr, p->udrc.raised);
avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
avr_io_setirqs(&p->io, AVR_IOCTL_UART_GETIRQ(p->name), UART_IRQ_COUNT, NULL);
// Only call callbacks when the value change...
p->io.irq[UART_IRQ_OUT_XOFF].flags |= IRQ_FLAG_FILTERED;
- p->io.irq[UART_IRQ_OUT_XON].flags |= IRQ_FLAG_FILTERED;
avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
- avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
// monitor code that reads the rxc flag, and delay it a bit
avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
- avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
- avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);
+ if (p->udrc.vector)
+ avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
+ if (p->r_ucsra)
+ avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
+ if (p->r_ubrrl)
+ avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);
}
projects / simavr / blobdiff