#endif
#include "sim_irq.h"
+#include "sim_interrupts.h"
#include "sim_cycle_timers.h"
struct avr_t;
-typedef uint8_t (*avr_io_read_t)(struct avr_t * avr, avr_io_addr_t addr, void * param);
-typedef void (*avr_io_write_t)(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param);
+typedef uint8_t (*avr_io_read_t)(
+ struct avr_t * avr,
+ avr_io_addr_t addr,
+ void * param);
+typedef void (*avr_io_write_t)(
+ struct avr_t * avr,
+ avr_io_addr_t addr,
+ uint8_t v,
+ void * param);
enum {
// SREG bit indexes
R_SREG = 32+0x3f,
// maximum number of IO registers, on normal AVRs
- MAX_IOs = 256 - 32, // minus 32 GP registers
+ MAX_IOs = 256, // Bigger AVRs need more than 256-32 (mega1280)
};
#define AVR_DATA_TO_IO(v) ((v) - 32)
// queue of io modules
struct avr_io_t *io_port;
+ // cycle timers tracking & delivery
avr_cycle_timer_pool_t cycle_timers;
-
- // interrupt vectors, and their enable/clear registers
- struct avr_int_vector_t * vector[64];
- uint8_t vector_count;
- uint8_t pending_wait; // number of cycles to wait for pending
- struct avr_int_vector_t * pending[64]; // needs to be >= vectors and a power of two
- uint8_t pending_w, pending_r; // fifo cursors
+ // interrupt vectors and delivery fifo
+ avr_int_table_t interrupts;
// DEBUG ONLY -- value ignored if CONFIG_SIMAVR_TRACE = 0
int trace : 1,
} avr_symbol_t;
// locate the maker for mcu "name" and allocates a new avr instance
-avr_t * avr_make_mcu_by_name(const char *name);
+avr_t *
+avr_make_mcu_by_name(
+ const char *name);
// initializes a new AVR instance. Will call the IO registers init(), and then reset()
-int avr_init(avr_t * avr);
+int
+avr_init(
+ avr_t * avr);
// resets the AVR, and the IO modules
-void avr_reset(avr_t * avr);
+void
+avr_reset(
+ avr_t * avr);
// run one cycle of the AVR, sleep if necessary
-int avr_run(avr_t * avr);
+int
+avr_run(
+ avr_t * avr);
// finish any pending operations
-void avr_terminate(avr_t * avr);
+void
+avr_terminate(
+ avr_t * avr);
// set an IO register to receive commands from the AVR firmware
// it's optional, and uses the ELF tags
-void avr_set_command_register(avr_t * avr, avr_io_addr_t addr);
+void
+avr_set_command_register(
+ avr_t * avr,
+ avr_io_addr_t addr);
// specify the "console register" -- output sent to this register
// is printed on the simulator console, without using a UART
-void avr_set_console_register(avr_t * avr, avr_io_addr_t addr);
+void
+avr_set_console_register(
+ avr_t * avr,
+ avr_io_addr_t addr);
// load code in the "flash"
-void avr_loadcode(avr_t * avr, uint8_t * code, uint32_t size, uint32_t address);
-
+void
+avr_loadcode(
+ avr_t * avr,
+ uint8_t * code,
+ uint32_t size,
+ uint32_t address);
/*
* these are accessors for avr->data but allows watchpoints to be set for gdb
* IO modules use that to set values to registers, and the AVR core decoder uses
* that to register "public" read by instructions.
*/
-void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v);
-uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr);
+void
+avr_core_watch_write(
+ avr_t *avr,
+ uint16_t addr,
+ uint8_t v);
+uint8_t
+avr_core_watch_read(
+ avr_t *avr,
+ uint16_t addr);
// called when the core has detected a crash somehow.
// this might activate gdb server
-void avr_sadly_crashed(avr_t *avr, uint8_t signal);
+void
+avr_sadly_crashed(
+ avr_t *avr,
+ uint8_t signal);
/*
#include "sim_io.h"
#include "sim_regbit.h"
-#include "sim_interrupts.h"
-#include "sim_cycle_timers.h"
#endif /*__SIM_AVR_H__*/