#endif
#include "sim_irq.h"
+#include "sim_interrupts.h"
#include "sim_cycle_timers.h"
+typedef uint32_t avr_flashaddr_t;
+
struct avr_t;
typedef uint8_t (*avr_io_read_t)(
struct avr_t * avr,
R_SREG = 32+0x3f,
// maximum number of IO registers, on normal AVRs
- MAX_IOs = 256 - 32, // minus 32 GP registers
+ MAX_IOs = 279, // Bigger AVRs need more than 256-32 (mega1280)
};
#define AVR_DATA_TO_IO(v) ((v) - 32)
#define AVR_IO_TO_DATA(v) ((v) + 32)
+/**
+ * Logging macros and associated log levels.
+ * The current log level is kept in avr->log.
+ */
+enum {
+ LOG_ERROR = 1,
+ LOG_WARNING,
+ LOG_TRACE,
+};
+#define AVR_LOG(avr, level, ...) \
+ do { \
+ if (avr->log >= level) \
+ fprintf(stdout, __VA_ARGS__); \
+ } while(0)
+
/*
* Core states.
*/
// not only to "cycles that runs" but also "cycles that might have run"
// like, sleeping.
avr_cycle_count_t cycle; // current cycle
+
+ /**
+ * Sleep requests are accumulated in sleep_usec until the minimum sleep value
+ * is reached, at which point sleep_usec is cleared and the sleep request
+ * is passed on to the operating system.
+ */
+ uint32_t sleep_usec;
// called at init time
void (*init)(struct avr_t * avr);
// called at init time (for special purposes like using a memory mapped file as flash see: simduino)
void (*special_init)(struct avr_t * avr);
- // called at termination time ( to clean special initalizations)
+ // called at termination time ( to clean special initializations)
void (*special_deinit)(struct avr_t * avr);
// called at reset time
void (*reset)(struct avr_t * avr);
// Mirror of the SREG register, to facilitate the access to bits
// in the opcode decoder.
- // This array is re-synthetized back/forth when SREG changes
+ // This array is re-synthesized back/forth when SREG changes
uint8_t sreg[8];
uint8_t i_shadow; // used to detect edges on I flag
* this is why you will see >>1 and <<1 in the decoder to handle jumps.
* It CAN be a little confusing, so concentrate, young grasshopper.
*/
- uint32_t pc;
+ avr_flashaddr_t pc;
/*
* callback when specific IO registers are read/written.
// queue of io modules
struct avr_io_t *io_port;
+ // cycle timers tracking & delivery
avr_cycle_timer_pool_t cycle_timers;
-
- // interrupt vectors, and their enable/clear registers
- struct avr_int_vector_t * vector[64];
- uint8_t vector_count;
- uint8_t pending_wait; // number of cycles to wait for pending
- struct avr_int_vector_t * pending[64]; // needs to be >= vectors and a power of two
- uint8_t pending_w, pending_r; // fifo cursors
+ // interrupt vectors and delivery fifo
+ avr_int_table_t interrupts;
// DEBUG ONLY -- value ignored if CONFIG_SIMAVR_TRACE = 0
- int trace : 1,
+ uint8_t trace : 1,
log : 2; // log level, default to 1
// Only used if CONFIG_SIMAVR_TRACE is defined
int
avr_init(
avr_t * avr);
+// Used by the cores, allocated a mutable avr_t from the const global
+avr_t *
+avr_core_allocate(
+ const avr_t * core,
+ uint32_t coreLen);
+
// resets the AVR, and the IO modules
void
avr_reset(
avr_t * avr,
uint8_t * code,
uint32_t size,
- uint32_t address);
+ avr_flashaddr_t address);
/*
- * these are accessors for avr->data but allows watchpoints to be set for gdb
+ * These are accessors for avr->data but allows watchpoints to be set for gdb
* IO modules use that to set values to registers, and the AVR core decoder uses
* that to register "public" read by instructions.
*/
/*
- * These are callbacks for the two 'main' bahaviour in simavr
+ * These are callbacks for the two 'main' behaviour in simavr
*/
void avr_callback_sleep_gdb(avr_t * avr, avr_cycle_count_t howLong);
void avr_callback_run_gdb(avr_t * avr);
#include "sim_io.h"
#include "sim_regbit.h"
-#include "sim_interrupts.h"
-#include "sim_cycle_timers.h"
#endif /*__SIM_AVR_H__*/