interrupts: Do not clear raised bit twice

[simavr] / tests / atmega48_disabled_timer.c

diff --git a/tests/atmega48_disabled_timer.c b/tests/atmega48_disabled_timer.c
index 5d0b069..332bbc9 100644 (file)
--- a/tests/atmega48_disabled_timer.c
+++ b/tests/atmega48_disabled_timer.c
@@ -7,14 +7,13 @@
 
 #include <avr/io.h>
 #include <avr/interrupt.h>
+#include <avr/sleep.h>
 
 #include "avr_mcu_section.h"
 AVR_MCU(F_CPU, "atmega48");
 
 ISR(TIMER0_COMPA_vect)
 {
-       TCCR0B = 0;
-       TCNT0 = 0;
 }
 
 int main(void)
@@ -24,10 +23,15 @@ int main(void)
        TIMSK0 |= (1 << OCIE0A);                    // Enable CTC interrupt
        OCR0A   = 0xAA;                             // CTC compare value
 
+       //TCCR0B |= (1 << CS00) | (1 << CS01);        // Start timer: clk/64
+
        sei();                                      // Enable global interrupts
 
        // here the interupts are enabled, but the interupt
        // vector should not be called
-       while(1)
-               ;
+       sleep_mode();
+
+       // this should not be reached
+       cli();
+       sleep_mode();
 }