X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;ds=inline;f=firmware%2Flib%2Fmsp430x1612.c;h=d577e502c680fa4f3bcd3e85ec4e10de1245e05f;hb=593dd80ba8c49c429e1f8d2d2185fa4ee47bda4d;hp=9d284157eea3f5e76a2061261fe46992ea42d8c3;hpb=bc3a26913581de36a8a26ed6b79d8ad77f1c739c;p=goodfet diff --git a/firmware/lib/msp430x1612.c b/firmware/lib/msp430x1612.c index 9d28415..d577e50 100644 --- a/firmware/lib/msp430x1612.c +++ b/firmware/lib/msp430x1612.c @@ -2,31 +2,35 @@ #include "platform.h" +#ifdef __MSPGCC__ +#include +#else #include #include #include +#endif //! Receive a byte. unsigned char serial0_rx(){ char c; - + while(!(IFG1&URXIFG0));//wait for a byte c = RXBUF0; IFG1&=~URXIFG0; U0TCTL &= ~URXSE; - + return c; } //! Receive a byte. unsigned char serial1_rx(){ char c; - + while(!(IFG2&URXIFG1));//wait for a byte c = RXBUF1; IFG2&=~URXIFG1; U1TCTL &= ~URXSE; - + return c; } @@ -52,7 +56,7 @@ void serial1_tx(unsigned char x){ //! Set the baud rate. void setbaud0(unsigned char rate){ - + //http://mspgcc.sourceforge.net/baudrate.html switch(rate){ case 1://9600 baud @@ -100,15 +104,15 @@ void setbaud1(unsigned char rate){ void msp430_init_uart0(){ /* RS232 */ - + P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD P3DIR |= BIT4; - + UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */ UTCTL0 = SSEL1; /* UCLK = MCLK */ - + setbaud0(0); - + ME1 &= ~USPIE0; /* USART1 SPI module disable */ ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */ @@ -116,24 +120,24 @@ void msp430_init_uart0(){ /* XXX Clear pending interrupts before enable!!! */ U0TCTL |= URXSE; - - + + //IE1 |= URXIE1; /* Enable USART1 RX interrupt */ } void msp430_init_uart1(){ - + /* RS232 */ P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */ P3DIR |= 0x40; /* Select P36 for output (UART1TX) */ P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */ - + UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */ UTCTL1 = SSEL1; /* UCLK = MCLK */ - + setbaud1(0); - + ME2 &= ~USPIE1; /* USART1 SPI module disable */ ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */ @@ -189,10 +193,10 @@ void msp430_init_dco() { #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8)) unsigned int compare, oldcapture = 0; unsigned int i; - + WDTCTL = WDTPW + WDTHOLD; //stop WDT - - + + DCOCTL=0xF0; //a4 //1100 @@ -200,12 +204,12 @@ void msp430_init_dco() { /* ACLK is devided by 4. RSEL=6 no division for MCLK and SSMCLK. XT2 is off. */ //BCSCTL1 = 0xa8; - + BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz crystal DCO frquenzy = 2,4576 MHz */ - + PLEDOUT|=PLEDPIN; - + BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */ for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */ asm("nop"); @@ -238,12 +242,12 @@ void msp430_init_dco() { /* -> Select next higher RSEL */ } } - + CCTL2 = 0; /* Stop CCR2 function */ TACTL = 0; /* Stop Timer_A */ BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */ - + PLEDOUT=~PLEDPIN; }