X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;ds=sidebyside;f=firmware%2Fapps%2Fspi%2Fspi.c;h=a5f72b862e1097bd3591377603d8e6060131701e;hb=c98b9c687e78bc3e3708074f286b481a35370a07;hp=93a41b9fd53bda2beeb666ad8b295a8892e888f0;hpb=92560226caf1a463eb144324978b0a390327e09e;p=goodfet diff --git a/firmware/apps/spi/spi.c b/firmware/apps/spi/spi.c index 93a41b9..a5f72b8 100644 --- a/firmware/apps/spi/spi.c +++ b/firmware/apps/spi/spi.c @@ -17,6 +17,7 @@ #define MISO BIT2 #define SCK BIT3 + //This could be more accurate. //Does it ever need to be? #define SPISPEED 0 @@ -35,8 +36,13 @@ void spisetup(){ P5OUT|=SS; P5DIR|=MOSI+SCK+SS; P5DIR&=~MISO; + + //Begin a new transaction. + P5OUT&=~SS; + P5OUT|=SS; } + //! Read and write an SPI bit. unsigned char spitrans8(unsigned char byte){ unsigned int bit; @@ -66,11 +72,81 @@ unsigned char spitrans8(unsigned char byte){ return byte; } + +//! Enable SPI writing +void spiflash_wrten(){ + P5OUT&=~SS; //Drop !SS to begin transaction. + spitrans8(0x04);//Write Disable + P5OUT|=SS; //Raise !SS to end transaction. + P5OUT&=~SS; //Drop !SS to begin transaction. + spitrans8(0x06);//Write Enable + P5OUT|=SS; //Raise !SS to end transaction. +} + + +//! Grab the SPI flash status byte. +unsigned char spiflash_status(){ + unsigned char c; + P5OUT|=SS; //Raise !SS to end transaction. + P5OUT&=~SS; //Drop !SS to begin transaction. + spitrans8(0x05);//GET STATUS + c=spitrans8(0xFF); + P5OUT|=SS; //Raise !SS to end transaction. + return c; +} + + +//! Grab the SPI flash status byte. +void spiflash_setstatus(unsigned char c){ + P5OUT&=~SS; //Drop !SS to begin transaction. + spitrans8(0x01);//SET STATUS + spitrans8(c); + P5OUT|=SS; //Raise !SS to end transaction. + //return c; +} + +//! Peek some blocks. +void spiflash_peek(unsigned char app, + unsigned char verb, + unsigned char len){ + register char blocks=(len>3?cmddata[3]:1); + unsigned char i,j; + + P5OUT&=~SS; //Drop !SS to begin transaction. + spitrans8(0x03);//Flash Read Command + len=3;//write 3 byte pointer + for(i=0;i