X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;ds=sidebyside;f=sump2%2Fimpl%2Fimpl_syn.prj;fp=sump2%2Fimpl%2Fimpl_syn.prj;h=97d267bb37ecc0c669b572bfb311e44df5c2b020;hb=b6ac52f611f53e96447a6bee178d418f14623985;hp=0000000000000000000000000000000000000000;hpb=bbafe3d7b73ed7bf085686eb333ea10a968bd40b;p=BML_sump2

diff --git a/sump2/impl/impl_syn.prj b/sump2/impl/impl_syn.prj
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+#-- Synopsys, Inc.
+#-- Project file C:\Users\shchen\Documents\shao\iCE_demo\to_ted\release\LED_rotation\impl\impl_syn.prj
+#project files
+
+add_file -verilog -lib work "../source/top.v" 
+add_file -verilog -lib work "../source/core.v" 
+add_file -verilog -lib work "../source/mesa2ctrl.v" 
+add_file -verilog -lib work "../source/mesa2lb.v" 
+add_file -verilog -lib work "../source/mesa_core.v" 
+add_file -verilog -lib work "../source/mesa_decode.v" 
+add_file -verilog -lib work "../source/spi_byte2bit.v" 
+add_file -verilog -lib work "../source/spi_prom.v" 
+add_file -verilog -lib work "../source/time_stamp.v" 
+add_file -verilog -lib work "../source/mesa_phy.v" 
+add_file -verilog -lib work "../source/mesa_uart.v" 
+add_file -verilog -lib work "../source/mesa_tx_uart.v" 
+add_file -verilog -lib work "../source/mesa_ascii2nibble.v" 
+add_file -verilog -lib work "../source/mesa_byte2ascii.v" 
+add_file -verilog -lib work "../source/sump2.v" 
+add_file -verilog -lib work "../source/top_pll.v" 
+add_file -constraint -lib work "../constraint/top.sdc"
+#implementation: "impl_Implmnt"
+impl -add impl_Implmnt -type fpga
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#device options
+set_option -technology SBTiCE40
+set_option -part iCE40HX1K
+set_option -package TQ144
+set_option -speed_grade 
+set_option -part_companion ""
+
+#compilation/mapping options
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file ./impl_Implmnt/impl.edf
+impl -active impl_Implmnt
+project -run synthesis -clean