X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-at91rm9200%2Fgpio.c;h=83c34747087bde8ed0a328ddaaa2db4032bbb049;hb=f6e6e883730aff2718610d3eba7608fcf73328ed;hp=2fd2ef583e4d4f596e43fac999f31f445276b6d7;hpb=e7de369050534025b33aab1033358bf47a577e4d;p=powerpc.git

diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index 2fd2ef583e..83c3474708 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -16,7 +16,7 @@
 
 #include <asm/io.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/hardware.h>
+#include <asm/hardware.h>
 #include <asm/arch/gpio.h>
 
 static const u32 pio_controller_offset[4] = {
@@ -159,6 +159,23 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 }
 EXPORT_SYMBOL(at91_set_deglitch);
 
+/*
+ * enable/disable the multi-driver; This is only valid for output and
+ * allows the output pin to run as an open collector output.
+ */
+int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
+{
+	void __iomem	*pio = pin_to_controller(pin);
+	unsigned	mask = pin_to_mask(pin);
+
+	if (!pio)
+		return -EINVAL;
+
+	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
+	return 0;
+}
+EXPORT_SYMBOL(at91_set_multi_drive);
+
 /*--------------------------------------------------------------------------*/
 
 
@@ -196,6 +213,84 @@ EXPORT_SYMBOL(at91_get_gpio_value);
 
 /*--------------------------------------------------------------------------*/
 
+#ifdef CONFIG_PM
+
+static u32 wakeups[BGA_GPIO_BANKS];
+static u32 backups[BGA_GPIO_BANKS];
+
+static int gpio_irq_set_wake(unsigned pin, unsigned state)
+{
+	unsigned	mask = pin_to_mask(pin);
+
+	pin -= PIN_BASE;
+	pin /= 32;
+
+	if (unlikely(pin >= BGA_GPIO_BANKS))
+		return -EINVAL;
+
+	if (state)
+		wakeups[pin] |= mask;
+	else
+		wakeups[pin] &= ~mask;
+
+	return 0;
+}
+
+void at91_gpio_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < BGA_GPIO_BANKS; i++) {
+		u32 pio = pio_controller_offset[i];
+
+		/*
+		 * Note: drivers should have disabled GPIO interrupts that
+		 * aren't supposed to be wakeup sources.
+		 * But that is not much good on ARM.....  disable_irq() does
+		 * not update the hardware immediately, so the hardware mask
+		 * (IMR) has the wrong value (not current, too much is
+		 * permitted).
+		 *
+		 * Our workaround is to disable all non-wakeup IRQs ...
+		 * which is exactly what correct drivers asked for in the
+		 * first place!
+		 */
+		backups[i] = at91_sys_read(pio + PIO_IMR);
+		at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]);
+		at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]);
+
+		if (!wakeups[i]) {
+			disable_irq_wake(AT91_ID_PIOA + i);
+			at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i));
+		} else {
+			enable_irq_wake(AT91_ID_PIOA + i);
+#ifdef CONFIG_PM_DEBUG
+			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
+#endif
+		}
+	}
+}
+
+void at91_gpio_resume(void)
+{
+	int i;
+
+	for (i = 0; i < BGA_GPIO_BANKS; i++) {
+		at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]);
+		at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]);
+	}
+
+	at91_sys_write(AT91_PMC_PCER,
+			  (1 << AT91_ID_PIOA)
+			| (1 << AT91_ID_PIOB)
+			| (1 << AT91_ID_PIOC)
+			| (1 << AT91_ID_PIOD));
+}
+
+#else
+#define gpio_irq_set_wake	NULL
+#endif
+
 
 /* Several AIC controller irqs are dispatched through this GPIO handler.
  * To use any AT91_PIN_* as an externally triggered IRQ, first call
@@ -235,6 +330,7 @@ static struct irqchip gpio_irqchip = {
 	.mask		= gpio_irq_mask,
 	.unmask		= gpio_irq_unmask,
 	.set_type	= gpio_irq_type,
+	.set_wake	= gpio_irq_set_wake,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
@@ -244,11 +340,12 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs
 	void __iomem	*pio;
 	u32		isr;
 
-	pio = (void __force __iomem *) desc->chipdata;
+	pio = desc->base;
 
 	/* temporarily mask (level sensitive) parent IRQ */
 	desc->chip->ack(irq);
 	for (;;) {
+		/* reading ISR acks the pending (edge triggered) GPIO interrupt */
 		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
 		if (!isr)
 			break;
@@ -257,8 +354,18 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs
 		gpio = &irq_desc[pin];
 
 		while (isr) {
-			if (isr & 1)
-				gpio->handle(pin, gpio, regs);
+			if (isr & 1) {
+				if (unlikely(gpio->disable_depth)) {
+					/*
+					 * The core ARM interrupt handler lazily disables IRQs so
+					 * another IRQ must be generated before it actually gets
+					 * here to be disabled on the GPIO controller.
+					 */
+					gpio_irq_mask(pin);
+				}
+				else
+					gpio->handle(pin, gpio, regs);
+			}
 			pin++;
 			gpio++;
 			isr >>= 1;
@@ -285,18 +392,19 @@ void __init at91_gpio_irq_setup(unsigned banks)
 		__raw_writel(~0, controller + PIO_IDR);
 
 		set_irq_data(id, (void *) pin);
-		set_irq_chipdata(id, (void __force *) controller);
+		set_irq_chipdata(id, controller);
 
 		for (i = 0; i < 32; i++, pin++) {
+			/*
+			 * Can use the "simple" and not "edge" handler since it's
+			 * shorter, and the AIC handles interupts sanely.
+			 */
 			set_irq_chip(pin, &gpio_irqchip);
 			set_irq_handler(pin, do_simple_IRQ);
 			set_irq_flags(pin, IRQF_VALID);
 		}
 
 		set_irq_chained_handler(id, gpio_irq_handler);
-
-		/* enable the PIO peripheral clock */
-		at91_sys_write(AT91_PMC_PCER, 1 << id);
 	}
 	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
 }