X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=board%2Fsandpoint%2Fearly_init.S;fp=board%2Fsandpoint%2Fearly_init.S;h=8b3e791017210fedf9a538c982fba74e76a3d48f;hb=2d59bb8882c8405bc400614a0db8b59db5a5fcc4;hp=07dafb716f915b2fdb37401973f67223fb000004;hpb=aabcd082f8ad221a487518ef33434919bbab868b;p=u-boot.git

diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S
index 07dafb7..8b3e791 100644
--- a/board/sandpoint/early_init.S
+++ b/board/sandpoint/early_init.S
@@ -37,6 +37,21 @@
   #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
 #endif
 
+
+#define UART1           0xfc004500
+#define UART1_IER       0xfc004501
+#define UART1_FCR       0xfc004502
+#define UART1_LCR       0xfc004503
+#define UART1_DCR       0xfc004511
+
+#define WM8(address,data) \
+	lis	r3, address@h; \
+	ori	r3, r3, address@l; \
+	li	r4, data; \
+	stb	r4, 0(r3); \
+	sync; \
+	isync;
+
 	.text
 
 	/* Values to program into memory controller registers */
@@ -105,6 +120,10 @@ tbl:	.long	MCCR1, MCCR1VAL
 early_init_f:
 	mflr	r10
 
+	WM8(0xfc004500,0x44);
+
+#if 0
+
 	/* basic memory controller configuration */
 	lis	r3, CONFIG_ADDR_HIGH
 	lis	r4, CONFIG_DATA_HIGH
@@ -147,6 +166,7 @@ delay:	bdnz	delay
 	/* set up stack pointer */
 	lis	r1, CFG_INIT_SP_OFFSET@h
 	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+#endif
 
 	mtlr	r10
 	blr