X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=drivers%2Fchar%2Frio%2Fcirrus.h;h=f4f837f868290a5e4baebfd61ae04e9b7f366c20;hb=026477c1141b67e98e3bd8bdedb7d4b88a3ecd09;hp=217ff09f2fa1697e965082a36b6510894bd6e643;hpb=e7de369050534025b33aab1033358bf47a577e4d;p=powerpc.git diff --git a/drivers/char/rio/cirrus.h b/drivers/char/rio/cirrus.h index 217ff09f2f..f4f837f868 100644 --- a/drivers/char/rio/cirrus.h +++ b/drivers/char/rio/cirrus.h @@ -40,215 +40,7 @@ #endif #define _cirrus_h 1 -#ifdef RTA -#define TO_UART RX -#define TO_DRIVER TX -#endif - -#ifdef HOST -#define TO_UART TX -#define TO_DRIVER RX -#endif -#ifdef RTA -/* Miscellaneous defines for CIRRUS addresses and related logic for - interrupts etc. -*/ -#define MAP(a) ((short *)(cirrus_base + (a))) -#define outp(a,b) (*MAP (a) =(b)) -#define inp(a) ((*MAP (a)) & 0xff) -#define CIRRUS_FIRST (short*)0x7300 -#define CIRRUS_SECOND (short*)0x7200 -#define CIRRUS_THIRD (short*)0x7100 -#define CIRRUS_FOURTH (short*)0x7000 -#define PORTS_ON_CIRRUS 4 -#define CIRRUS_FIFO_SIZE 12 -#define SPACE 0x20 -#define TAB 0x09 -#define LINE_FEED 0x0a -#define CARRIAGE_RETURN 0x0d -#define BACKSPACE 0x08 -#define SPACES_IN_TABS 8 -#define SEND_ESCAPE 0x00 -#define START_BREAK 0x81 -#define TIMER_TICK 0x82 -#define STOP_BREAK 0x83 -#define BASE(a) ((a) < 4 ? (short*)CIRRUS_FIRST : ((a) < 8 ? (short *)CIRRUS_SECOND : ((a) < 12 ? (short*)CIRRUS_THIRD : (short *)CIRRUS_FOURTH))) -#define txack1 ((short *)0x7104) -#define rxack1 ((short *)0x7102) -#define mdack1 ((short *)0x7106) -#define txack2 ((short *)0x7006) -#define rxack2 ((short *)0x7004) -#define mdack2 ((short *)0x7100) -#define int_latch ((short *) 0x7800) -#define int_status ((short *) 0x7c00) -#define tx1_pending 0x20 -#define rx1_pending 0x10 -#define md1_pending 0x40 -#define tx2_pending 0x02 -#define rx2_pending 0x01 -#define md2_pending 0x40 -#define module1_bits 0x07 -#define module1_modern 0x08 -#define module2_bits 0x70 -#define module2_modern 0x80 -#define module_blank 0xf -#define rs232_d25 0x0 -#define rs232_rj45 0x1 -#define rs422_d25 0x3 -#define parallel 0x5 - -#define CLK0 0x00 -#define CLK1 0x01 -#define CLK2 0x02 -#define CLK3 0x03 -#define CLK4 0x04 - -#define CIRRUS_REVC 0x42 -#define CIRRUS_REVE 0x44 - -#define TURNON 1 -#define TURNOFF 0 - -/* The list of CIRRUS registers. - NB. These registers are relative values on 8 bit boundaries whereas - on the RTA's the CIRRUS registers are on word boundaries. Use pointer - arithmetic (short *) to obtain the real addresses required */ -#define ccr 0x05 /* Channel Command Register */ -#define ier 0x06 /* Interrupt Enable Register */ -#define cor1 0x08 /* Channel Option Register 1 */ -#define cor2 0x09 /* Channel Option Register 2 */ -#define cor3 0x0a /* Channel Option Register 3 */ -#define cor4 0x1e /* Channel Option Register 4 */ -#define cor5 0x1f /* Channel Option Register 5 */ - -#define ccsr 0x0b /* Channel Control Status Register */ -#define rdcr 0x0e /* Receive Data Count Register */ -#define tdcr 0x12 /* Transmit Data Count Register */ -#define mcor1 0x15 /* Modem Change Option Register 1 */ -#define mcor2 0x16 /* Modem Change Option Regsiter 2 */ - -#define livr 0x18 /* Local Interrupt Vector Register */ -#define schr1 0x1a /* Special Character Register 1 */ -#define schr2 0x1b /* Special Character Register 2 */ -#define schr3 0x1c /* Special Character Register 3 */ -#define schr4 0x1d /* Special Character Register 4 */ - -#define rtr 0x20 /* Receive Timer Register */ -#define rtpr 0x21 /* Receive Timeout Period Register */ -#define lnc 0x24 /* Lnext character */ - -#define rivr 0x43 /* Receive Interrupt Vector Register */ -#define tivr 0x42 /* Transmit Interrupt Vector Register */ -#define mivr 0x41 /* Modem Interrupt Vector Register */ -#define gfrcr 0x40 /* Global Firmware Revision code Reg */ -#define ricr 0x44 /* Receive Interrupting Channel Reg */ -#define ticr 0x45 /* Transmit Interrupting Channel Reg */ -#define micr 0x46 /* Modem Interrupting Channel Register */ - -#define gcr 0x4b /* Global configuration register */ -#define misr 0x4c /* Modem interrupt status register */ - -#define rbusr 0x59 -#define tbusr 0x5a -#define mbusr 0x5b - -#define eoir 0x60 /* End Of Interrupt Register */ -#define rdsr 0x62 /* Receive Data / Status Register */ -#define tdr 0x63 /* Transmit Data Register */ -#define svrr 0x67 /* Service Request Register */ - -#define car 0x68 /* Channel Access Register */ -#define mir 0x69 /* Modem Interrupt Register */ -#define tir 0x6a /* Transmit Interrupt Register */ -#define rir 0x6b /* Receive Interrupt Register */ -#define msvr1 0x6c /* Modem Signal Value Register 1 */ -#define msvr2 0x6d /* Modem Signal Value Register 2 */ -#define psvr 0x6f /* Printer Signal Value Register */ - -#define tbpr 0x72 /* Transmit Baud Rate Period Register */ -#define tcor 0x76 /* Transmit Clock Option Register */ - -#define rbpr 0x78 /* Receive Baud Rate Period Register */ -#define rber 0x7a /* Receive Baud Rate Extension Register */ -#define rcor 0x7c /* Receive Clock Option Register */ -#define ppr 0x7e /* Prescalar Period Register */ - -/* Misc registers used for forcing the 1400 out of its reset woes */ -#define airl 0x6d -#define airm 0x6e -#define airh 0x6f -#define btcr 0x66 -#define mtcr 0x6c -#define tber 0x74 - -#endif /* #ifdef RTA */ - - -/* Bit fields for particular registers */ - -/* GCR */ -#define GCR_SERIAL 0x00 /* Configure as serial channel */ -#define GCR_PARALLEL 0x80 /* Configure as parallel channel */ - -/* RDSR - when status read from FIFO */ -#define RDSR_BREAK 0x08 /* Break received */ -#define RDSR_TIMEOUT 0x80 /* No new data timeout */ -#define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */ -#define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */ -#define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */ - -/* PPR */ -#define PPR_DEFAULT 0x31 /* Default value - for a 25Mhz clock gives - a timeout period of 1ms */ - -/* LIVR */ -#define LIVR_EXCEPTION 0x07 /* Receive exception interrupt */ - -/* CCR */ -#define CCR_RESET 0x80 /* Reset channel */ -#define CCR_CHANGE 0x4e /* COR's have changed - NB always change all - COR's */ -#define CCR_WFLUSH 0x82 /* Flush transmit FIFO and TSR / THR */ - -#define CCR_SENDSC1 0x21 /* Send special character one */ -#define CCR_SENDSC2 0x22 /* Send special character two */ -#define CCR_SENDSC3 0x23 /* Send special character three */ -#define CCR_SENDSC4 0x24 /* Send special character four */ - -#define CCR_TENABLE 0x18 /* Enable transmitter */ -#define CCR_TDISABLE 0x14 /* Disable transmitter */ -#define CCR_RENABLE 0x12 /* Enable receiver */ -#define CCR_RDISABLE 0x11 /* Disable receiver */ - -#define CCR_READY 0x00 /* CCR is ready for another command */ - -/* CCSR */ -#define CCSR_TXENABLE 0x08 /* Transmitter enable */ -#define CCSR_RXENABLE 0x80 /* Receiver enable */ -#define CCSR_TXFLOWOFF 0x04 /* Transmit flow off */ -#define CCSR_TXFLOWON 0x02 /* Transmit flow on */ - -/* SVRR */ -#define SVRR_RECEIVE 0x01 /* Receive interrupt pending */ -#define SVRR_TRANSMIT 0x02 /* Transmit interrupt pending */ -#define SVRR_MODEM 0x04 /* Modem interrupt pending */ - -/* CAR */ -#define CAR_PORTS 0x03 /* Bit fields for ports */ - -/* IER */ -#define IER_MODEM 0x80 /* Change in modem status */ -#define IER_RECEIVE 0x10 /* Good data / data exception */ -#define IER_TRANSMITR 0x04 /* Transmit ready (FIFO empty) */ -#define IER_TRANSMITE 0x02 /* Transmit empty */ -#define IER_TIMEOUT 0x01 /* Timeout on no data */ - -#define IER_DEFAULT 0x94 /* Default values */ -#define IER_PARALLEL 0x84 /* Default for Parallel */ -#define IER_EMPTY 0x92 /* Transmitter empty rather than ready */ - -/* COR1 - Driver only */ -#define COR1_INPCK 0x10 /* Check parity of received characters */ +/* Bit fields for particular registers shared with driver */ /* COR1 - driver and RTA */ #define COR1_ODD 0x80 /* Odd parity */ @@ -364,35 +156,6 @@ #define MSVR1_HOST 0xf3 /* The bits the host wants */ -/* MSVR2 */ -#define MSVR2_DSR 0x02 /* DSR output pin (DTR on Cirrus) */ - -/* MCOR */ -#define MCOR_CD 0x80 /* CD (DSR on Cirrus) */ -#define MCOR_RTS 0x40 /* RTS (CTS on Cirrus) */ -#define MCOR_RI 0x20 /* RI */ -#define MCOR_DTR 0x10 /* DTR (CD on Cirrus) */ - -#define MCOR_DEFAULT (MCOR_CD | MCOR_RTS | MCOR_RI | MCOR_DTR) -#define MCOR_FULLMODEM MCOR_DEFAULT -#define MCOR_RJ45 (MCOR_CD | MCOR_RTS | MCOR_DTR) -#define MCOR_RESTRICTED (MCOR_CD | MCOR_RTS) - -/* More MCOR - H/W Handshake (flowcontrol) stuff */ -#define MCOR_THRESH8 0x08 /* eight characters then we stop */ -#define MCOR_THRESH9 0x09 /* nine characters then we stop */ -#define MCOR_THRESH10 0x0A /* ten characters then we stop */ -#define MCOR_THRESH11 0x0B /* eleven characters then we stop */ - -#define MCOR_THRESHBITS 0x0F /* mask for ANDing out the above */ - -#define MCOR_THRESHOLD MCOR_THRESH9 /* MUST BE GREATER THAN COR3_THRESHOLD */ - - -/* RTPR */ -#define RTPR_DEFAULT 0x02 /* Default */ - - /* Defines for the subscripts of a CONFIG packet */ #define CONFIG_COR1 1 /* Option register 1 */ #define CONFIG_COR2 2 /* Option register 2 */ @@ -406,19 +169,6 @@ #define CONFIG_TXBAUD 10 /* Tx baud rate */ #define CONFIG_RXBAUD 11 /* Rx baud rate */ -/* Port status stuff */ -#define IDLE_CLOSED 0 /* Closed */ -#define IDLE_OPEN 1 /* Idle open */ -#define IDLE_BREAK 2 /* Idle on break */ - -/* Subscript of MODEM STATUS packet */ -#define MODEM_VALUE 3 /* Current values of handshake pins */ -/* Subscript of SBREAK packet */ -#define BREAK_LENGTH 1 /* Length of a break in slices of 0.01 seconds - 0 = stay on break until an EBREAK command - is sent */ - - #define PRE_EMPTIVE 0x80 /* Pre-emptive bit in command field */ /* Packet types going from Host to remote - with the exception of OPEN, MOPEN,