X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fsky2.h;h=dce955c76f3cc18f8006d28022af2a7168f626b0;hb=72f2afb8a6858edd9335cd158eb21053a0c2c39a;hp=7943dd42ac94778f6f437a7925cfda8e5c0c8222;hpb=6e23231b6509f17a251e6dfddb607d300680ac25;p=powerpc.git diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 7943dd42ac..dce955c76f 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -5,14 +5,22 @@ #define _SKY2_H /* PCI config registers */ -#define PCI_DEV_REG1 0x40 -#define PCI_DEV_REG2 0x44 -#define PCI_DEV_STATUS 0x7c -#define PCI_OS_PCI_X (1<<26) +enum { + PCI_DEV_REG1 = 0x40, + PCI_DEV_REG2 = 0x44, + PCI_DEV_STATUS = 0x7c, + PCI_DEV_REG3 = 0x80, + PCI_DEV_REG4 = 0x84, + PCI_DEV_REG5 = 0x88, +}; -#define PEX_LNK_STAT 0xf2 -#define PEX_UNC_ERR_STAT 0x104 -#define PEX_DEV_CTRL 0xe8 +enum { + PEX_DEV_CAP = 0xe4, + PEX_DEV_CTRL = 0xe8, + PEX_DEV_STA = 0xea, + PEX_LNK_STAT = 0xf2, + PEX_UNC_ERR_STAT= 0x104, +}; /* Yukon-2 */ enum pci_dev_reg_1 { @@ -37,6 +45,25 @@ enum pci_dev_reg_2 { PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ }; +/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ +enum pci_dev_reg_4 { + /* (Link Training & Status State Machine) */ + P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ + /* (Active State Power Management) */ + P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ + P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ + P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ + P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ + + P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ + P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ + P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ + P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ + P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ + P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN + | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, +}; + #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ PCI_STATUS_SIG_SYSTEM_ERROR | \ @@ -507,6 +534,16 @@ enum { }; #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) +/* Q_F 32 bit Flag Register */ +enum { + F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ + F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ + F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ + F_WM_REACHED = 1<<25, /* Watermark reached */ + F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ + F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ + F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ +}; /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ enum { @@ -909,10 +946,12 @@ enum { PHY_BCOM_ID1_C0 = 0x6044, PHY_BCOM_ID1_C5 = 0x6047, - PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ - PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ - PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ + PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ + PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ }; /* Advertisement register bits */ @@ -1777,11 +1816,15 @@ struct sky2_status_le { u8 opcode; } __attribute((packed)); +struct tx_ring_info { + struct sk_buff *skb; + DECLARE_PCI_UNMAP_ADDR(mapaddr); + u16 idx; +}; + struct ring_info { struct sk_buff *skb; dma_addr_t mapaddr; - u16 maplen; - u16 idx; }; struct sky2_port { @@ -1791,7 +1834,7 @@ struct sky2_port { u32 msg_enable; spinlock_t tx_lock ____cacheline_aligned_in_smp; - struct ring_info *tx_ring; + struct tx_ring_info *tx_ring; struct sky2_tx_le *tx_le; u16 tx_cons; /* next le to check */ u16 tx_prod; /* next le to use */ @@ -1807,6 +1850,7 @@ struct sky2_port { u16 rx_put; /* next le index to use */ u16 rx_pending; u16 rx_last_put; + u16 rx_bufsize; #ifdef SKY2_VLAN_TAG_USED u16 rx_tag; struct vlan_group *vlgrp; @@ -1823,15 +1867,18 @@ struct sky2_port { u8 rx_csum; u8 wol; - struct tasklet_struct phy_task; struct net_device_stats net_stats; + + struct work_struct phy_task; + struct semaphore phy_sema; }; struct sky2_hw { void __iomem *regs; struct pci_dev *pdev; - u32 intr_mask; struct net_device *dev[2]; + spinlock_t hw_lock; + u32 intr_mask; int pm_cap; u8 chip_id; @@ -1842,8 +1889,6 @@ struct sky2_hw { struct sky2_status_le *st_le; u32 st_idx; dma_addr_t st_dma; - - spinlock_t phy_lock; }; /* Register accessor for memory mapped device */ @@ -1862,14 +1907,6 @@ static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) return readb(hw->regs + reg); } -/* This should probably go away, bus based tweeks suck */ -static inline int is_pciex(const struct sky2_hw *hw) -{ - u32 status; - pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status); - return (status & PCI_OS_PCI_X) == 0; -} - static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) { writel(val, hw->regs + reg); @@ -1914,4 +1951,25 @@ static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); } + +/* PCI config space access */ +static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) +{ + return sky2_read32(hw, Y2_CFG_SPC + reg); +} + +static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) +{ + return sky2_read16(hw, Y2_CFG_SPC + reg); +} + +static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) +{ + sky2_write32(hw, Y2_CFG_SPC + reg, val); +} + +static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) +{ + sky2_write16(hw, Y2_CFG_SPC + reg, val); +} #endif