X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=firmware%2Fapps%2Fchipcon%2Fchipcon.c;h=fac551cbc67640786e75dced12a5934ba9bd9a85;hb=c59e00857cea5dba2c38dcb5070594a237c297a6;hp=8d4abca0dfe301cb06b903d9cfaadb31cc36e24d;hpb=ad4619be9d5a713318196ead4aeb6000e7d3f0e3;p=goodfet diff --git a/firmware/apps/chipcon/chipcon.c b/firmware/apps/chipcon/chipcon.c index 8d4abca..fac551c 100644 --- a/firmware/apps/chipcon/chipcon.c +++ b/firmware/apps/chipcon/chipcon.c @@ -56,12 +56,28 @@ void ccsetup(){ //P5REN=0xFF; } + +/* 33 cycle critical region +0000000e : + e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles + 12: 31 00 + 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles + 18: d2 c3 31 00 bic.b #1, &0x0031 ;4 + 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4 + 20: f2 e2 31 00 xor.b #8, &0x0031 ;4 + 24: f2 e2 31 00 xor.b #8, &0x0031 ;4 + 28: f2 e2 31 00 xor.b #8, &0x0031 ;4 + 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4 + 30: 30 41 ret +*/ + + //! Initialize the debugger void ccdebuginit(){ //Port output BUT NOT DIRECTION is set at start. P5OUT|=MOSI+SCK+RST; - delay(30); //So the beginning is ready for glitching. + //delay(30); //So the beginning is ready for glitching. //Two positive debug clock pulses while !RST is low. //Take RST low, pulse twice, then high. @@ -154,7 +170,6 @@ void cchandle(unsigned char app, txdata(app,verb,0); break; case START://enter debugger - //ccsetup(); //interferes with glitching ccdebuginit(); txdata(app,verb,0); break;