X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=firmware%2Finclude%2Fjtagarm7.h;h=74016a1fa8ee224dac6243dc1e09998dca0e9c31;hb=7709570a1640165f33552ce52284c4fca2a54d91;hp=a67a88c8e99e950d270163022c545bbcc133e43c;hpb=285dbbf59c01923e155759d01f6f4f0e09878d9b;p=goodfet

diff --git a/firmware/include/jtagarm7.h b/firmware/include/jtagarm7.h
index a67a88c..74016a1 100644
--- a/firmware/include/jtagarm7.h
+++ b/firmware/include/jtagarm7.h
@@ -2,71 +2,47 @@
   \brief JTAG handler functions for the ARM7TDMI family of processors
 */
 
-#include "jtag.h"
+#ifndef JTAGARM7_H
+#define JTAGARM7_H
 
+#include "app.h"
+
+#define JTAGARM7 0x13
 
 #define JTAGSTATE_ARM 0         // bit 4 on dbg status reg is low
 #define JTAGSTATE_THUMB 1
 
-#define ARMTCKTOCK  CLRTCK; PLEDOUT^=PLEDPIN; SETTCK; PLEDOUT^=PLEDPIN;
-// ASSUME RUN-TEST/IDLE STATE
-#define SHIFT_IR    SETTMS;TCKTOCK;TCKTOCK;CLRTMS;TCKTOCK;TCKTOCK;
-#define SHIFT_DR    SETTMS;TCKTOCK;CLRTMS;TCKTOCK;TCKTOCK;
-
-
-
-unsigned char current_chain;
-unsigned char current_dbgstate = -1;
-//unsigned char last_halt_debug_state = -1;
-//unsigned long last_halt_pc = -1;
-
-
-//void jtag_goto_shift_ir();
-//void jtag_goto_shift_dr();
-//void jtag_reset_to_runtest_idle();
-//void jtag_arm_tcktock();
-
-
-// JTAGARM7TDMI Commands
-
-//! Write data to address.
-unsigned long jtagarm7tdmi_writemem(unsigned long adr, unsigned long data);
-//! Read data from address
-unsigned long jtagarm7tdmi_readmem(unsigned long adr);
-
-//! Halt the CPU
-unsigned long jtagarm7tdmi_haltcpu();
-//! Release the CPU
-unsigned long jtagarm7tdmi_releasecpu();
-
-//! Set the program counter.
-void jtagarm7tdmi_setpc(unsigned long adr);
-
-//! Write data to address.
-unsigned long jtagarm7tdmi_writeflash(unsigned long adr, unsigned long data);
-
+// JTAG TAP states
+#define Exit2_DR 0x0
+#define Exit_DR 0x1
+#define Shift_DR 0x2
+#define Pause_DR 0x3
+#define Select_IR 0x4
+#define Update_DR 0x5
+#define Capture_DR 0x6
+#define Select_DR 0x7
+#define Exit2_IR 0x8
+#define Exit_IR 0x9
+#define Shift_IR 0xa
+#define Pause_IR 0xb
+#define RunTest_Idle 0xc
+#define Update_IR 0xd
+#define Capture_IR 0xe
+#define Test_Reset 0xf
+
+// JTAGARM7 Commands
 
 //! Start JTAG
 void jtagarm7tdmi_start(void);
-//! Reset TAP State Machine
-void jtagarm7tdmi_resettap();
-
-//! ARM-specific JTAG bit-transfer
-unsigned long jtagarmtransn(unsigned long word, unsigned char bitcount, unsigned char lsb, unsigned char end, unsigned char retidle);
-
-//! Grab debug register - Expect chain 2 to be selected
-unsigned long jtagarm7tdmi_get_dbgstate() ;
-//! Grab the core ID.
-unsigned long jtagarm7tdmi_idcode();
-//!  Connect Bypass Register to TDO/TDI
-unsigned char jtagarm7tdmi_bypass();
-//!  Connect the appropriate scan chain to TDO/TDI
-unsigned long jtagarm7tdmi_scan_intest(int n);
+
 //!  Set a 32-bit ARM register
 void jtagarm7tdmi_set_register(unsigned long reg, unsigned long val);
 //!  Get a 32-bit ARM register
 unsigned long jtagarm7tdmi_get_register(unsigned long reg);
 
+//!  Shift an arbitrary number of bits, using an array of uchars
+uint8_t* jtag_trans_many(uint8_t *word, uint8_t bitcount, enum eTransFlags flags);
+
 // ARM7TDMI-specific pins
 // DBGRQ - GoodFET Pin 8
 #define DBGRQ   TST
@@ -129,10 +105,9 @@ The least significant bit of the instruction register is scanned in and scanned
 
 
 //JTAGARM7TDMI commands
-#define JTAGARM7_RESETTARGET                0x86
-#define JTAGARM7_GET_REGISTER               0x87
-#define JTAGARM7_SET_REGISTER               0x88
-#define JTAGARM7_DEBUG_INSTR                0x89
+#define JTAGARM7_GET_REGISTER               0x8d
+#define JTAGARM7_SET_REGISTER               0x8e
+#define JTAGARM7_DEBUG_INSTR                0x8f
 // Really ARM specific stuff
 #define JTAGARM7_SET_IR                     0x90
 #define JTAGARM7_WAIT_DBG                   0x91
@@ -141,7 +116,11 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAGARM7_SCANCHAIN1                 0x94
 #define JTAGARM7_EICE_READ                  0x95
 #define JTAGARM7_EICE_WRITE                 0x96
+#define JTAGARM7_IR_SIZE                    0x9f
+#define JTAGARM7_SCAN_N_SIZE                0x9e
 
+#define JTAGARM_SCAN1_MANY                  0x9d
+#define JTAG_DR_SHIFT_MANY                  0x9c
 
 // for deeper understanding, read the instruction cycle timing section of: 
 //      http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
@@ -171,8 +150,12 @@ The least significant bit of the instruction register is scanned in and scanned
 #define THUMB_READ_REG              THUMB_INSTR_STR_R0_r0
 #define THUMB_INSTR_MOV_R0_PC       0x46b846b8L
 #define THUMB_INSTR_MOV_PC_R0       0x46474647L
+#define THUMB_INSTR_MOV_HiLo        0x46404640L
+#define THUMB_INSTR_MOV_LoHi        0x46804680L
 #define THUMB_INSTR_BX_PC           0x47784778L
 #define THUMB_INSTR_NOP             0x1c001c00L
+#define THUMB_SWAP_HiLo             0
+#define THUMB_SWAP_LoHi             1
 #define ARM_REG_PC                  15
 
 #define JTAG_ARM7TDMI_DBG_DBGACK    1
@@ -180,4 +163,9 @@ The least significant bit of the instruction register is scanned in and scanned
 #define JTAG_ARM7TDMI_DBG_IFEN      4
 #define JTAG_ARM7TDMI_DBG_cgenL     8
 #define JTAG_ARM7TDMI_DBG_TBIT      16
+extern app_t const jtagarm7_app;
+extern unsigned char g_jtag_ir_size;
+extern unsigned char g_jtagarm_scan_n_bitsize;
+
+#endif // JTAGARM7_H