X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=simavr%2Fcores%2Fsim_mega128.c;h=ce142a55ff4a7e40725fe763008bc2e4063d4f6d;hb=40c40d5dfccc12d788daa20dc4008bfba34fab8d;hp=7c0bf50e77fe107a868d68e41e9ebf2890ddb674;hpb=5268a8b5858aae31aeb6160e8dd071af1c030d67;p=simavr

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 7c0bf50..ce142a5 100644
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -41,9 +41,9 @@ void m128_reset(struct avr_t * avr);
 #include "avr/iom128.h"
 
 /*
- * This is a template for all of the 128 devices, hopefuly
+ * This is a template for all of the 128 devices, hopefully
  */
-struct mcu_t {
+const struct mcu_t {
 	avr_t          core;
 	avr_eeprom_t 	eeprom;
 	avr_flash_t 	selfprog;
@@ -107,6 +107,8 @@ struct mcu_t {
 
 		.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 		.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+		.ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), 	// 1 bits
 
 		.r_ucsra = UCSR0A,
 		.r_ucsrb = UCSR0B,
@@ -136,6 +138,8 @@ struct mcu_t {
 
 		.txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
 		.rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+		.ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), 	// 1 bits
 
 		.r_ucsra = UCSR1A,
 		.r_ucsrb = UCSR1B,
@@ -164,6 +168,8 @@ struct mcu_t {
 					AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
 					AVR_IO_REGBIT(ADMUX, MUX4),},
 		.ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+		.ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256 },
+
 		.adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
 		.r_adcsra = ADCSRA,
 		.aden = AVR_IO_REGBIT(ADCSRA, ADEN),
@@ -177,6 +183,30 @@ struct mcu_t {
 		//.r_adcsrb = ADCSRB,
 		// .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
 
+		.muxmode = {
+			[0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+			[2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+			[4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
+			[6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
+
+			[ 8] = AVR_ADC_DIFF(0, 0,  10), [ 9] = AVR_ADC_DIFF(1, 0,  10),
+			[10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
+			[12] = AVR_ADC_DIFF(2, 2,  10), [13] = AVR_ADC_DIFF(3, 2,  10),
+			[14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
+
+			[16] = AVR_ADC_DIFF(0, 1,   1), [17] = AVR_ADC_DIFF(1, 1,   1),
+			[18] = AVR_ADC_DIFF(2, 1,   1), [19] = AVR_ADC_DIFF(3, 1,   1),
+			[20] = AVR_ADC_DIFF(4, 1,   1), [21] = AVR_ADC_DIFF(5, 1,   1),
+			[22] = AVR_ADC_DIFF(6, 1,   1), [23] = AVR_ADC_DIFF(7, 1,   1),
+
+			[24] = AVR_ADC_DIFF(0, 2,   1), [25] = AVR_ADC_DIFF(1, 2,   1),
+			[26] = AVR_ADC_DIFF(2, 2,   1), [27] = AVR_ADC_DIFF(3, 2,   1),
+			[28] = AVR_ADC_DIFF(4, 2,   1), [29] = AVR_ADC_DIFF(5, 2,   1),
+
+			[30] = AVR_ADC_REF(1230),	// 1.1V
+			[31] = AVR_ADC_REF(0),		// GND
+		},
+
 		.adc = {
 			.enable = AVR_IO_REGBIT(ADCSRA, ADIE),
 			.raised = AVR_IO_REGBIT(ADCSRA, ADIF),
@@ -209,7 +239,7 @@ struct mcu_t {
 		.comp = {
 			[AVR_TIMER_COMPA] = {
 				.r_ocr = OCR0,
-				.com = { AVR_IO_REGBIT(TCCR0, COM00), AVR_IO_REGBIT(TCCR0, COM01) },
+				.com = AVR_IO_REGBITS(TCCR0, COM00, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, PB4),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK, OCIE0),
@@ -225,9 +255,9 @@ struct mcu_t {
 					AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
 		.wgm_op = {
 			[0] = AVR_TIMER_WGM_NORMAL16(),
-			// TODO: 1 PWM phase corret 8bit
-			// 		 2 PWM phase corret 9bit
-			//       3 PWM phase corret 10bit
+			// TODO: 1 PWM phase correct 8bit
+			// 		 2 PWM phase correct 9bit
+			//       3 PWM phase correct 10bit
 			[4] = AVR_TIMER_WGM_CTC(),
 			[5] = AVR_TIMER_WGM_FASTPWM8(),
 			[6] = AVR_TIMER_WGM_FASTPWM9(),
@@ -245,6 +275,9 @@ struct mcu_t {
 		.r_icrh = ICR1H,
 		.r_tcnth = TCNT1H,
 
+		.ices = AVR_IO_REGBIT(TCCR1B, ICES1),
+		.icp = AVR_IO_REGBIT(PORTD, 4),
+
 		.overflow = {
 			.enable = AVR_IO_REGBIT(TIMSK, TOIE1),
 			.raised = AVR_IO_REGBIT(TIFR, TOV1),
@@ -259,7 +292,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPA] = {
 				.r_ocr = OCR1AL,
 				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
-				.com = { AVR_IO_REGBIT(TCCR1A, COM1A0), AVR_IO_REGBIT(TCCR1A, COM1A1) },
+				.com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, PB5),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
@@ -270,7 +303,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPB] = {
 				.r_ocr = OCR1BL,
 				.r_ocrh = OCR1BH,
-				.com = { AVR_IO_REGBIT(TCCR1A, COM1B0), AVR_IO_REGBIT(TCCR1A, COM1B1) },
+				.com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, PB6),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
@@ -281,7 +314,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPC] = {
 				.r_ocr = OCR1CL,
 				.r_ocrh = OCR1CH,
-				.com = { AVR_IO_REGBIT(TCCR1A, COM1C0), AVR_IO_REGBIT(TCCR1A, COM1C1) },
+				.com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer2
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
@@ -314,7 +347,7 @@ struct mcu_t {
 		.comp = {
 			[AVR_TIMER_COMPA] = {
 				.r_ocr = OCR2,
-				.com = { AVR_IO_REGBIT(TCCR2, COM20), AVR_IO_REGBIT(TCCR2, COM21) },
+				.com = AVR_IO_REGBITS(TCCR2, COM20, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK, OCIE2),
@@ -330,15 +363,15 @@ struct mcu_t {
 					AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
 		.wgm_op = {
 			[0] = AVR_TIMER_WGM_NORMAL16(),
-			// TODO: 1 PWM phase corret 8bit
-			//       2 PWM phase corret 9bit
-			//       3 PWM phase corret 10bit
+			// TODO: 1 PWM phase correct 8bit
+			//       2 PWM phase correct 9bit
+			//       3 PWM phase correct 10bit
 			[4] = AVR_TIMER_WGM_CTC(),
 			[5] = AVR_TIMER_WGM_FASTPWM8(),
 			[6] = AVR_TIMER_WGM_FASTPWM9(),
 			[7] = AVR_TIMER_WGM_FASTPWM10(),
-			// TODO: 8 PWM phase and freq corret ICR
-			//       9 PWM phase and freq corret OCR
+			// TODO: 8 PWM phase and freq correct ICR
+			//       9 PWM phase and freq correct OCR
 			//       10
 			//       11
 			[12] = AVR_TIMER_WGM_ICCTC(),
@@ -353,6 +386,9 @@ struct mcu_t {
 		.r_icrh = ICR3H,
 		.r_tcnth = TCNT3H,
 
+		.ices = AVR_IO_REGBIT(TCCR3B, ICES3),
+		.icp = AVR_IO_REGBIT(PORTE, 7),
+
 		.overflow = {
 			.enable = AVR_IO_REGBIT(ETIMSK, TOIE3),
 			.raised = AVR_IO_REGBIT(ETIFR, TOV3),
@@ -362,7 +398,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPA] = {
 				.r_ocr = OCR3AL,
 				.r_ocrh = OCR3AH,	// 16 bits timers have two bytes of it
-				.com = { AVR_IO_REGBIT(TCCR3A, COM3A0), AVR_IO_REGBIT(TCCR3A, COM3A1) },
+				.com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE3),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
@@ -373,7 +409,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPB] = {
 				.r_ocr = OCR3BL,
 				.r_ocrh = OCR3BH,
-				.com = { AVR_IO_REGBIT(TCCR3A, COM3B0), AVR_IO_REGBIT(TCCR3A, COM3B1) },
+				.com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE4),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
@@ -384,7 +420,7 @@ struct mcu_t {
 			[AVR_TIMER_COMPC] = {
 				.r_ocr = OCR3CL,
 				.r_ocrh = OCR3CH,
-				.com = { AVR_IO_REGBIT(TCCR3A, COM3C0), AVR_IO_REGBIT(TCCR3A, COM3C1) },
+				.com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE5),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
@@ -436,7 +472,7 @@ struct mcu_t {
 
 		.twi = {
 			.enable = AVR_IO_REGBIT(TWCR, TWIE),
-			.raised = AVR_IO_REGBIT(TWSR, TWINT),
+			.raised = AVR_IO_REGBIT(TWCR, TWINT),
 			.vector = TWI_vect,
 		},
 	},
@@ -445,7 +481,7 @@ struct mcu_t {
 
 static avr_t * make()
 {
-        return &mcu_mega128.core;
+	return avr_core_allocate(&mcu_mega128.core, sizeof(struct mcu_t));
 }
 
 avr_kind_t mega128 = {