X-Git-Url: http://git.rot13.org/?a=blobdiff_plain;f=src%2Frc632.h;h=c7690ed0bc42f204f59600b403f68db126642180;hb=a91cd3d9e2a4e985c63850679e8242c6d08fed08;hp=0bd5b00a6166d0c3a4178c8e81ad310009a87cfa;hpb=7600eb5ebbb8ac0f7532e7e7ae6cb5d4dc29d30b;p=librfid

diff --git a/src/rc632.h b/src/rc632.h
index 0bd5b00..c7690ed 100644
--- a/src/rc632.h
+++ b/src/rc632.h
@@ -79,13 +79,27 @@ enum rc632_reg_command {
 	RC632_CMD_RECEIVE		= 0x16,
 	RC632_CMD_LOAD_KEY		= 0x19,
 	RC632_CMD_TRANSMIT		= 0x1a,
-	RC632_CMD_TRANSCIEVE		= 0x1e,
+	RC632_CMD_TRANSCEIVE		= 0x1e,
 	RC632_CMD_STARTUP		= 0x3f,
 };
 
+enum rc632_reg_interrupt {
+	RC632_INT_LOALERT		= 0x01,
+	RC632_INT_HIALERT		= 0x02,
+	RC632_INT_IDLE			= 0x04,
+	RC632_INT_RX			= 0x08,
+	RC632_INT_TX			= 0x10,
+	RC632_INT_TIMER			= 0x20,
+	RC632_INT_SET			= 0x80,
+};
+
 enum rc632_reg_control {
+	RC632_CONTROL_FIFO_FLUSH	= 0x01,
+	RC632_CONTROL_TIMER_START	= 0x02,
+	RC632_CONTROL_TIMER_STOP	= 0x04,
 	RC632_CONTROL_CRYPTO1_ON	= 0x08,
 	RC632_CONTROL_POWERDOWN		= 0x10,
+	RC632_CONTROL_STANDBY		= 0x20,
 };
 
 enum rc632_reg_error_flag {
@@ -116,7 +130,7 @@ enum rc632_reg_coder_control {
 	RC632_CDRCTRL_TXCD_14443A	= 0x01,
 	RC632_CDRCTRL_TXCD_ICODE_STD	= 0x04,
 
-#define RC632_CDRDTRL_RATE_MASK		0x38
+#define RC632_CDRCTRL_RATE_MASK		0x38
 	RC632_CDRCTRL_RATE_848K		= 0x00,
 	RC632_CDRCTRL_RATE_424K		= 0x08,
 	RC632_CDRCTRL_RATE_212K		= 0x10,
@@ -151,6 +165,7 @@ enum rc632_reg_rx_control1 {
 	RC632_RXCTRL1_ISO15693		= 0x08,
 	RC632_RXCTRL1_ISO14443		= 0x10,
 
+#define RC632_RXCTRL1_SUBCP_MASK	0xe0
 	RC632_RXCTRL1_SUBCP_1		= 0x00,
 	RC632_RXCTRL1_SUBCP_2		= 0x20,
 	RC632_RXCTRL1_SUBCP_4		= 0x40,
@@ -207,4 +222,26 @@ enum rc632_reg_channel_redundancy {
 	RC632_CR_CRC3309		= 0x20,
 };
 
+enum rc632_reg_timer_control {
+	RC632_TMR_START_TX_BEGIN	= 0x01,
+	RC632_TMR_START_TX_END		= 0x02,
+	RC632_TMR_STOP_RX_BEGIN		= 0x04,
+	RC632_TMR_STOP_RX_END		= 0x08,
+};
+ 
+enum rc632_reg_timer_irq {
+	RC632_IRQ_LO_ALERT		= 0x01,
+	RC632_IRQ_HI_ALERT		= 0x02,
+	RC632_IRQ_IDLE			= 0x04,
+	RC632_IRQ_RX			= 0x08,
+	RC632_IRQ_TX			= 0x10,
+	RC632_IRQ_TIMER			= 0x20,
+
+	RC632_IRQ_SET			= 0x80,
+};
 
+enum rc632_reg_secondary_status {
+	RC632_SEC_ST_TMR_RUNNING	= 0x80,
+	RC632_SEC_ST_E2_READY		= 0x40,
+	RC632_SEC_ST_CRC_READY		= 0x20,
+};