clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30

clk: tegra: Convert CCLKG mux to mux + clock divider on Tegra30

Some of the CCLKG parents aren't accessible via device tree because they
are created as non-DT clocks. Apparently there is no reason to define
these clocks in that manner, hence convert CCLKG mux to mux + clock
divider to remove the non-DT parent clocks. Now it is possible to request
all of CCLKG parents from device tree, which is necessary for the CPUFreq
driver.

Note that CCLKG bypasses clock divider only if PLLX is selected as the
parent, hence previous CCLKG parents definition was incorrect.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>