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(parent: d5842f0) | patch
clk: tegra: Don't enable already enabled PLLs
authorDmitry Osipenko <digetx@gmail.com>
Tue, 14 Aug 2018 19:04:46 +0000 (22:04 +0300)
committerDmitry Osipenko <digetx@gmail.com>
Sat, 9 Feb 2019 19:15:23 +0000 (22:15 +0300)
commit599f269b2dc48394a6e66fb007b331d1a37c5a30
tree65d7f50bf8b90bb99b3be65e0870c4759f617d9ftree | snapshot
parentd5842f0ad9f1b99ed1bb4ae52087473cc2de8da0commit | diff
clk: tegra: Don't enable already enabled PLLs

Initially Common Clock Framework isn't aware of the clock-enable status,
this results in enabling of clocks that were enabled by bootloader. This
is not a big deal for a regular clock-gates, but for PLL's it may have
some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
clock) may result in extra long period of PLL re-locking.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
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