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(parent: 599f269) | patch
clk: tegra20: Enable lock-status polling for PLLs
authorDmitry Osipenko <digetx@gmail.com>
Mon, 13 Aug 2018 20:53:58 +0000 (23:53 +0300)
committerDmitry Osipenko <digetx@gmail.com>
Sat, 9 Feb 2019 19:15:24 +0000 (22:15 +0300)
commit6c5f066c33966370318b276c9d2a460756270876
treec1a282ca89dc33ea17b4a6e3da0adfdc30b13f8atree | snapshot
parent599f269b2dc48394a6e66fb007b331d1a37c5a30commit | diff
clk: tegra20: Enable lock-status polling for PLLs

Currently all PLL's on Tegra20 use a hardcoded delay despite of having
a lock-status bit. The lock-status polling was disabled ~7 years ago
because PLLE was failing to lock and was a suspicion that other PLLs
might be faulty too. Other PLLs are okay, hence enable the lock-status
polling for them. This reduces delay of any operation that require PLL
to lock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | history
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