+static int eti_b1_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
+ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
+ int ret;
+
+#ifdef CONFIG_SND_AT91_SOC_ETI_SLAVE
+ unsigned int rate;
+ int cmr_div, period;
+
+ /* set codec DAI configuration */
+ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * The SSC clock dividers depend on the sample rate. The CMR.DIV
+ * field divides the system master clock MCK to drive the SSC TK
+ * signal which provides the codec BCLK. The TCMR.PERIOD and
+ * RCMR.PERIOD fields further divide the BCLK signal to drive
+ * the SSC TF and RF signals which provide the codec DACLRC and
+ * ADCLRC clocks.
+ *
+ * The dividers were determined through trial and error, where a
+ * CMR.DIV value is chosen such that the resulting BCLK value is
+ * divisible, or almost divisible, by (2 * sample rate), and then
+ * the TCMR.PERIOD or RCMR.PERIOD is BCLK / (2 * sample rate) - 1.
+ */
+ rate = params_rate(params);
+
+ switch (rate) {
+ case 8000:
+ cmr_div = 25; /* BCLK = 60MHz/(2*25) = 1.2MHz */
+ period = 74; /* LRC = BCLK/(2*(74+1)) = 8000Hz */
+ break;
+ case 32000:
+ cmr_div = 7; /* BCLK = 60MHz/(2*7) ~= 4.28571428MHz */
+ period = 66; /* LRC = BCLK/(2*(66+1)) = 31982.942Hz */
+ break;
+ case 48000:
+ cmr_div = 13; /* BCLK = 60MHz/(2*13) ~= 2.3076923MHz */
+ period = 23; /* LRC = BCLK/(2*(23+1)) = 48076.923Hz */
+ break;
+ default:
+ printk(KERN_WARNING "unsupported rate %d on ETI-B1 board\n", rate);
+ return -EINVAL;
+ }
+
+ /* set the MCK divider for BCLK */
+ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, AT91SSC_CMR_DIV, cmr_div);
+ if (ret < 0)
+ return ret;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ /* set the BCLK divider for DACLRC */
+ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai,
+ AT91SSC_TCMR_PERIOD, period);
+ } else {
+ /* set the BCLK divider for ADCLRC */
+ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai,
+ AT91SSC_RCMR_PERIOD, period);
+ }
+ if (ret < 0)
+ return ret;
+
+#else /* CONFIG_SND_AT91_SOC_ETI_SLAVE */
+ /*
+ * Codec in Master Mode.
+ */
+
+ /* set codec DAI configuration */
+ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0)
+ return ret;
+
+#endif /* CONFIG_SND_AT91_SOC_ETI_SLAVE */
+
+ return 0;
+}
+