Add support for Geforce 6100 and related chipsets (PCI device id 0x024x)
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
case NV_ARCH_20:
case NV_ARCH_30:
default:
case NV_ARCH_20:
case NV_ARCH_30:
default:
- if (((par->Chipset & 0xffff) == 0x01A0) ||
+ if ((par->Chipset & 0xfff0) == 0x0240) {
+ state->arbitration0 = 256;
+ state->arbitration1 = 0x0480;
+ } else if (((par->Chipset & 0xffff) == 0x01A0) ||
((par->Chipset & 0xffff) == 0x01f0)) {
nForceUpdateArbitrationSettings(VClk,
pixelDepth * 8,
((par->Chipset & 0xffff) == 0x01f0)) {
nForceUpdateArbitrationSettings(VClk,
pixelDepth * 8,
break;
case 0x0160:
case 0x01D0:
break;
case 0x0160:
case 0x01D0:
NV_WR32(par->PMC, 0x1700,
NV_RD32(par->PFB, 0x020C));
NV_WR32(par->PMC, 0x1704, 0);
NV_WR32(par->PMC, 0x1700,
NV_RD32(par->PFB, 0x020C));
NV_WR32(par->PMC, 0x1704, 0);
if(((par->Chipset & 0xfff0)
!= 0x0160) &&
((par->Chipset & 0xfff0)
if(((par->Chipset & 0xfff0)
!= 0x0160) &&
((par->Chipset & 0xfff0)
+ != 0x0220) &&
+ ((par->Chipset & 0xfff0)
+ != 0x240))
NV_WR32(par->PGRAPH,
0x6900 + i*4,
NV_RD32(par->PFB,
NV_WR32(par->PGRAPH,
0x6900 + i*4,
NV_RD32(par->PFB,
case 0x0210:
case 0x0220:
case 0x0230:
case 0x0210:
case 0x0220:
case 0x0230:
case 0x0290:
case 0x0390:
arch = NV_ARCH_40;
case 0x0290:
case 0x0390:
arch = NV_ARCH_40;