[PATCH] KVM: Handle p5 mce msrs

This allows plan9 to get a little further booting.

Signed-off-by: Michael Riepe <michael@mr511.de>
Signed-off-by: Avi Kivity <avi@qumranet.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/drivers/kvm/svm.c b/drivers/kvm/svm.c
index 59c930f..9ec8763 100644 (file)
--- a/drivers/kvm/svm.c
+++ b/drivers/kvm/svm.c
@@ -1073,6 +1073,8 @@ static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_ru
 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
 {
        switch (ecx) {
+       case MSR_IA32_P5_MC_ADDR:
+       case MSR_IA32_P5_MC_TYPE:
        case MSR_IA32_MC0_CTL:
        case MSR_IA32_MCG_STATUS:
        case MSR_IA32_MCG_CAP:

diff --git a/drivers/kvm/vmx.c b/drivers/kvm/vmx.c
index 2d7c6d6..983a15b 100644 (file)
--- a/drivers/kvm/vmx.c
+++ b/drivers/kvm/vmx.c
@@ -359,6 +359,8 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
        case MSR_IA32_SYSENTER_ESP:
                data = vmcs_read32(GUEST_SYSENTER_ESP);
                break;
+       case MSR_IA32_P5_MC_ADDR:
+       case MSR_IA32_P5_MC_TYPE:
        case MSR_IA32_MC0_CTL:
        case MSR_IA32_MCG_STATUS:
        case MSR_IA32_MCG_CAP: