--- /dev/null
+FlashAprom /nuc/cheali-charger/src/hardware/nuvoton-M0517/targets/imaxB6-clone/cheali-charger-imaxB6-clone_2.01-e10.3.12-20210623_nuvoton-M0517.bin
+FlashAprom /nuc/cheali-charger/src/hardware/nuvoton-M0517/targets/imaxB6-clone/cheali-charger-imaxB6-clone_2.01-e10.3.12-20210705_nuvoton-M0517.bin
--- /dev/null
+openocd -s /nuc/cheali-charger/utils/M0517_flash_tools/tcl -f target_M0517_rpi.cfg -f M0517_flash.tcl -f M0517_unlock.tcl
--- /dev/null
+#
+# Config for using Raspberry Pi's expansion header
+#
+# This is best used with a fast enough buffer but also
+# is suitable for direct connection if the target voltage
+# matches RPi's 3.3V and the cable is short enough.
+#
+# Do not forget the GND connection, pin 6 of the expansion header.
+#
+
+adapter driver bcm2835gpio
+
+bcm2835gpio_peripheral_base 0x3F000000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for stock 700MHz
+# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
+bcm2835gpio_speed_coeffs 146203 36
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# swd gpio pins swclk swio
+bcm2835gpio_swd_nums 27 17
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+#bcm2835gpio_trst_num 22
+#reset_config trst_only
+
+bcm2835gpio_srst_num 22
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
+
+#adapter speed 100
+transport select swd
+
+## test which chip this is
+#swd newdap chip cpu -enable
+#dap create chip.dap -chain-position chip.cpu
+#target create chip.cpu cortex_m -dap chip.dap
+#
+#init
+
--- /dev/null
+# script for nuvoton M0517 OpenOCD 0.10 on Linux using Raspberry Pi gpio pins
+
+# IMAX B6 clone pinout - Raspberry Pi
+#
+# DAT - pin 11 (gpio 17)
+# CLK - pin 13 (gpio 27)
+# RST - pin 15 (gpio 22)
+# GND - pin 6 GND
+# VCC - pin 2 5V
+#
+
+adapter driver bcm2835gpio
+
+bcm2835gpio_peripheral_base 0x3F000000
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on system clock, calibrated for stock 700MHz
+# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
+bcm2835gpio_speed_coeffs 146203 36
+
+# Each of the SWD lines need a gpio number set: swclk swdio
+# swd gpio pins swclk swio
+bcm2835gpio_swd_nums 27 17
+
+# If you define trst or srst, use appropriate reset_config
+# Header pin numbers: TRST - 26, SRST - 18
+
+#bcm2835gpio_trst_num 22
+#reset_config trst_only
+
+bcm2835gpio_srst_num 22
+# reset_config srst_only srst_push_pull
+
+# or if you have both connected,
+# reset_config trst_and_srst srst_push_pull
+
+transport select swd
+
+
+set _CHIPNAME M0517
+set _ENDIAN little
+set _WORKAREASIZE 0x1000
+set _CPUTAPID 0x0bb11477
+
+
+swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap
+
+$_CHIPNAME.cpu configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 1000
+adapter srst delay 100
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}