ARM: dts: tegra30: apalis: Setup voltage regulators for DVFS

Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>

diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index c18f6f6..dba35e1 100644 (file)
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -890,8 +890,11 @@
 
                                vddctrl_reg: vddctrl {
                                        regulator-name = "+V1.0_VDD_CPU";
-                                       regulator-min-microvolt = <1150000>;
-                                       regulator-max-microvolt = <1150000>;
+                                       regulator-min-microvolt = <800000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-coupled-with = <&core_vdd_reg>;
+                                       regulator-coupled-max-spread = <300000>;
+                                       regulator-max-step-microvolt = <100000>;
                                        regulator-always-on;
                                };
 
@@ -1019,13 +1022,16 @@
                };
 
                /* SW: +V1.2_VDD_CORE */
-               regulator@60 {
+               core_vdd_reg: regulator@60 {
                        compatible = "ti,tps62362";
                        reg = <0x60>;
 
                        regulator-name = "tps62362-vout";
                        regulator-min-microvolt = <900000>;
                        regulator-max-microvolt = <1400000>;
+                       regulator-coupled-with = <&vddctrl_reg>;
+                       regulator-coupled-max-spread = <300000>;
+                       regulator-max-step-microvolt = <100000>;
                        regulator-boot-on;
                        regulator-always-on;
                        ti,vsel0-state-low;
@@ -1174,4 +1180,11 @@
                         <&tegra_car TEGRA30_CLK_EXTERN1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
+
+       cpus {
+               cpu0: cpu@0 {
+                       cpu-supply = <&vddctrl_reg>;
+                       core-supply = <&core_vdd_reg>;
+               };
+       };
 };