unsigned long);
int scan_threshold;
unsigned long int_parm;
- void **input_sbal_addr_array;
- void **output_sbal_addr_array;
+ struct qdio_buffer **input_sbal_addr_array;
+ struct qdio_buffer **output_sbal_addr_array;
struct qdio_outbuf_state *output_sbal_state_array;
};
.endm
/* VECTOR LOAD MULTIPLE */
-.macro VLM vfrom, vto, disp, base
+.macro VLM vfrom, vto, disp, base, hint=3
VX_NUM v1, \vfrom
VX_NUM v3, \vto
GR_NUM b2, \base /* Base register */
.word 0xE700 | ((v1&15) << 4) | (v3&15)
.word (b2 << 12) | (\disp)
- MRXBOPC 0, 0x36, v1, v3
+ MRXBOPC \hint, 0x36, v1, v3
.endm
/* VECTOR STORE MULTIPLE */
-.macro VSTM vfrom, vto, disp, base
+.macro VSTM vfrom, vto, disp, base, hint=3
VX_NUM v1, \vfrom
VX_NUM v3, \vto
GR_NUM b2, \base /* Base register */
.word 0xE700 | ((v1&15) << 4) | (v3&15)
.word (b2 << 12) | (\disp)
- MRXBOPC 0, 0x3E, v1, v3
+ MRXBOPC \hint, 0x3E, v1, v3
.endm
/* VECTOR PERMUTE */
mvc 0(16,%r1),__LC_BOOT_CLOCK
larl %r13,.LPG1 # get base
lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
- lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
- # move IPL device to lowcore
larl %r0,boot_vdso_data
stg %r0,__LC_VDSO_PER_CPU
#
#include <linux/memory.h>
#include <linux/compat.h>
#include <linux/start_kernel.h>
-#include <linux/version.h>
#include <asm/ipl.h>
#include <asm/facility.h>
{
unsigned long start_pfn = PFN_UP(__pa(_end));
-#ifdef CONFIG_DMA_API_DEBUG
- /*
- * DMA_API_DEBUG code stumbles over addresses from the
- * range [PARMAREA_END, _stext]. Mark the memory as reserved
- * so it is not used for CONFIG_DMA_API_DEBUG=y.
- */
- memblock_reserve(0, PFN_PHYS(start_pfn));
-#else
memblock_reserve(0, PARMAREA_END);
memblock_reserve((unsigned long)_stext, PFN_PHYS(start_pfn)
- (unsigned long)_stext);
-#endif
}
static void __init setup_memory(void)
return STACK_RND_MASK << PAGE_SHIFT;
}
-/*
- * Top of mmap area (just below the process stack).
- *
- * Leave at least a ~32 MB hole.
- */
-#define MIN_GAP (32*1024*1024)
-#define MAX_GAP (STACK_TOP/6*5)
-
static inline int mmap_is_legacy(struct rlimit *rlim_stack)
{
if (current->personality & ADDR_COMPAT_LAYOUT)
struct rlimit *rlim_stack)
{
unsigned long gap = rlim_stack->rlim_cur;
+ unsigned long pad = stack_maxrandom_size() + stack_guard_gap;
+ unsigned long gap_min, gap_max;
+
+ /* Values close to RLIM_INFINITY can overflow. */
+ if (gap + pad > gap)
+ gap += pad;
+
+ /*
+ * Top of mmap area (just below the process stack).
+ * Leave at least a ~32 MB hole.
+ */
+ gap_min = 32 * 1024 * 1024UL;
+ gap_max = (STACK_TOP / 6) * 5;
+
+ if (gap < gap_min)
+ gap = gap_min;
+ else if (gap > gap_max)
+ gap = gap_max;
- if (gap < MIN_GAP)
- gap = MIN_GAP;
- else if (gap > MAX_GAP)
- gap = MAX_GAP;
- gap &= PAGE_MASK;
- return STACK_TOP - stack_maxrandom_size() - rnd - gap;
+ return PAGE_ALIGN(STACK_TOP - gap - rnd);
}
unsigned long
struct zpci_dev *zdev = to_zpci(pdev);
int idx;
- if (!pci_resource_len(pdev, bar))
+ if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
return NULL;
idx = zdev->bars[bar].map_idx;
}
}
+#ifdef CONFIG_PCI_IOV
+static struct resource iov_res = {
+ .name = "PCI IOV res",
+ .start = 0,
+ .end = -1,
+ .flags = IORESOURCE_MEM,
+};
+#endif
+
static void zpci_map_resources(struct pci_dev *pdev)
{
resource_size_t len;
(resource_size_t __force) pci_iomap(pdev, i, 0);
pdev->resource[i].end = pdev->resource[i].start + len - 1;
}
+
+#ifdef CONFIG_PCI_IOV
+ i = PCI_IOV_RESOURCES;
+
+ for (; i < PCI_SRIOV_NUM_BARS + PCI_IOV_RESOURCES; i++) {
+ len = pci_resource_len(pdev, i);
+ if (!len)
+ continue;
+ pdev->resource[i].parent = &iov_res;
+ }
+#endif
}
static void zpci_unmap_resources(struct pci_dev *pdev)
}
static void setup_storage_lists(struct qdio_q *q, struct qdio_irq *irq_ptr,
- void **sbals_array, int i)
+ struct qdio_buffer **sbals_array, int i)
{
struct qdio_q *prev;
int j;
struct qdio_initialize *qdio_init)
{
struct qdio_q *q;
- void **input_sbal_array = qdio_init->input_sbal_addr_array;
- void **output_sbal_array = qdio_init->output_sbal_addr_array;
+ struct qdio_buffer **input_sbal_array = qdio_init->input_sbal_addr_array;
+ struct qdio_buffer **output_sbal_array = qdio_init->output_sbal_addr_array;
struct qdio_outbuf_state *output_sbal_state_array =
qdio_init->output_sbal_state_array;
int i;
init_data.output_handler = qeth_qdio_output_handler;
init_data.queue_start_poll_array = queue_start_poll;
init_data.int_parm = (unsigned long) card;
- init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
- init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
+ init_data.input_sbal_addr_array = in_sbal_ptrs;
+ init_data.output_sbal_addr_array = out_sbal_ptrs;
init_data.output_sbal_state_array = card->qdio.out_bufstates;
init_data.scan_threshold =
(card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
id->input_handler = zfcp_qdio_int_resp;
id->output_handler = zfcp_qdio_int_req;
id->int_parm = (unsigned long) qdio;
- id->input_sbal_addr_array = (void **) (qdio->res_q);
- id->output_sbal_addr_array = (void **) (qdio->req_q);
+ id->input_sbal_addr_array = qdio->res_q;
+ id->output_sbal_addr_array = qdio->req_q;
id->scan_threshold =
QDIO_MAX_BUFFERS_PER_Q - ZFCP_QDIO_MAX_SBALS_PER_REQ * 2;
}