cores: Updated for 16 bits timers and ADCs

Also made a macro for EXTINT declarations.

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/cores/sim_megax4.c b/simavr/cores/sim_megax4.c
index 0dc259b..d0dcb80 100644 (file)
--- a/simavr/cores/sim_megax4.c
+++ b/simavr/cores/sim_megax4.c
@@ -37,8 +37,10 @@ void mx4_init(struct avr_t * avr)
        avr_ioport_init(avr, &mcu->portd);
        avr_uart_init(avr, &mcu->uart0);
        avr_uart_init(avr, &mcu->uart1);
-       avr_timer8_init(avr, &mcu->timer0);
-       avr_timer8_init(avr, &mcu->timer2);
+       avr_adc_init(avr, &mcu->adc);
+       avr_timer_init(avr, &mcu->timer0);
+       avr_timer_init(avr, &mcu->timer1);
+       avr_timer_init(avr, &mcu->timer2);
        avr_spi_init(avr, &mcu->spi);
        avr_twi_init(avr, &mcu->twi);
 }

diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index 328b364..f851097 100644 (file)
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -28,7 +28,8 @@
 #include "avr_extint.h"
 #include "avr_ioport.h"
 #include "avr_uart.h"
-#include "avr_timer8.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
 #include "avr_spi.h"
 #include "avr_twi.h"
 
@@ -44,7 +45,8 @@ struct mcu_t {
        avr_extint_t    extint;
        avr_ioport_t    porta, portb, portc, portd;
        avr_uart_t              uart0,uart1;
-       avr_timer8_t    timer0,timer2;
+       avr_adc_t               adc;
+       avr_timer_t             timer0,timer1,timer2;
        avr_spi_t               spi;
        avr_twi_t               twi;
 };
@@ -164,10 +166,40 @@ struct mcu_t SIM_CORENAME = {
                        .vector = USART1_UDRE_vect,
                },
        },
-
+       .adc = {
+               .r_admux = ADMUX,
+               .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
+                                       AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
+                                       AVR_IO_REGBIT(ADMUX, MUX4),},
+               .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+               .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
+               .r_adcsra = ADCSRA,
+               .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
+               .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
+               .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
+               .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
+
+               .r_adch = ADCH,
+               .r_adcl = ADCL,
+
+               .r_adcsrb = ADCSRB,
+               .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+
+               .adc = {
+                       .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
+                       .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
+                       .vector = ADC_vect,
+               },
+       },
        .timer0 = {
                .name = '0',
                .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
                .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
@@ -191,9 +223,59 @@ struct mcu_t SIM_CORENAME = {
                        .vector = TIMER0_COMPB_vect,
                },
        },
+       .timer1 = {
+               .name = '1',
+               .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
+               .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
+                                       AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL16(),
+                       [4] = AVR_TIMER_WGM_CTC(),
+                       [5] = AVR_TIMER_WGM_FASTPWM(),
+                       [6] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
+               .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
+               .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
+
+               .r_ocra = OCR1AL,
+               .r_ocrb = OCR1BL,
+               .r_tcnt = TCNT1L,
+
+               .r_ocrah = OCR1AH,      // 16 bits timers have two bytes of it
+               .r_ocrbh = OCR1BH,
+               .r_tcnth = TCNT1H,
+
+               .overflow = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
+                       .raised = AVR_IO_REGBIT(TIFR1, TOV1),
+                       .vector = TIMER1_OVF_vect,
+               },
+               .compa = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+                       .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+                       .vector = TIMER1_COMPA_vect,
+               },
+               .compb = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+                       .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+                       .vector = TIMER1_COMPB_vect,
+               },
+               .icr = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
+                       .raised = AVR_IO_REGBIT(TIFR1, ICF1),
+                       .vector = TIMER1_CAPT_vect,
+               },
+       },
        .timer2 = {
                .name = '2',
                .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
                .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
                .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 

diff --git a/simavr/cores/sim_megax8.c b/simavr/cores/sim_megax8.c
index 3a22318..0a9f782 100644 (file)
--- a/simavr/cores/sim_megax8.c
+++ b/simavr/cores/sim_megax8.c
@@ -35,8 +35,10 @@ void mx8_init(struct avr_t * avr)
        avr_ioport_init(avr, &mcu->portc);
        avr_ioport_init(avr, &mcu->portd);
        avr_uart_init(avr, &mcu->uart);
-       avr_timer8_init(avr, &mcu->timer0);
-       avr_timer8_init(avr, &mcu->timer2);
+       avr_adc_init(avr, &mcu->adc);
+       avr_timer_init(avr, &mcu->timer0);
+       avr_timer_init(avr, &mcu->timer1);
+       avr_timer_init(avr, &mcu->timer2);
        avr_spi_init(avr, &mcu->spi);
        avr_twi_init(avr, &mcu->twi);
 }

diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 3124df9..b18293c 100644 (file)
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -28,7 +28,8 @@
 #include "avr_extint.h"
 #include "avr_ioport.h"
 #include "avr_uart.h"
-#include "avr_timer8.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
 #include "avr_spi.h"
 #include "avr_twi.h"
 
@@ -44,7 +45,8 @@ struct mcu_t {
        avr_extint_t    extint;
        avr_ioport_t    portb,portc,portd;
        avr_uart_t              uart;
-       avr_timer8_t    timer0,timer2;
+       avr_adc_t               adc;
+       avr_timer_t             timer0,timer1,timer2;
        avr_spi_t               spi;
        avr_twi_t               twi;
 };
@@ -128,11 +130,40 @@ struct mcu_t SIM_CORENAME = {
                        .vector = USART_UDRE_vect,
                },
        },
+       .adc = {
+               .r_admux = ADMUX,
+               .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
+                                       AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
+               .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+               .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
+               .r_adcsra = ADCSRA,
+               .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
+               .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
+               .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
+               .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
 
+               .r_adch = ADCH,
+               .r_adcl = ADCL,
+
+               .r_adcsrb = ADCSRB,
+               .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+
+               .adc = {
+                       .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
+                       .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
+                       .vector = ADC_vect,
+               },
+       },
        .timer0 = {
                .name = '0',
                .disabled = AVR_IO_REGBIT(PRR,PRTIM0),
                .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
                .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
@@ -156,10 +187,61 @@ struct mcu_t SIM_CORENAME = {
                        .vector = TIMER0_COMPB_vect,
                },
        },
+       .timer1 = {
+               .name = '1',
+               .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
+               .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
+                                       AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL16(),
+                       [4] = AVR_TIMER_WGM_CTC(),
+                       [5] = AVR_TIMER_WGM_FASTPWM(),
+                       [6] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
+               .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
+               .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
+
+               .r_ocra = OCR1AL,
+               .r_ocrb = OCR1BL,
+               .r_tcnt = TCNT1L,
+
+               .r_ocrah = OCR1AH,      // 16 bits timers have two bytes of it
+               .r_ocrbh = OCR1BH,
+               .r_tcnth = TCNT1H,
+
+               .overflow = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
+                       .raised = AVR_IO_REGBIT(TIFR1, TOV1),
+                       .vector = TIMER1_OVF_vect,
+               },
+               .compa = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+                       .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+                       .vector = TIMER1_COMPA_vect,
+               },
+               .compb = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+                       .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+                       .vector = TIMER1_COMPB_vect,
+               },
+               .icr = {
+                       .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
+                       .raised = AVR_IO_REGBIT(TIFR1, ICF1),
+                       .vector = TIMER1_CAPT_vect,
+               },
+       },
        .timer2 = {
                .name = '2',
                .disabled = AVR_IO_REGBIT(PRR,PRTIM2),
                .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
+
                .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
                .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 

diff --git a/simavr/cores/sim_tiny13.c b/simavr/cores/sim_tiny13.c
index baba938..3cad3ad 100644 (file)
--- a/simavr/cores/sim_tiny13.c
+++ b/simavr/cores/sim_tiny13.c
@@ -25,7 +25,7 @@
 #include "sim_core_declare.h"
 #include "avr_eeprom.h"
 #include "avr_ioport.h"
-#include "avr_timer8.h"
+#include "avr_timer.h"
 
 #define _AVR_IO_H_
 #define __ASSEMBLER__
@@ -39,7 +39,7 @@ static struct mcu_t {
        avr_t core;
        avr_eeprom_t    eeprom;
        avr_ioport_t    portb;
-       avr_timer8_t    timer0;
+       avr_timer_t             timer0;
 } mcu = {
        .core = {
                .mmcu = "attiny13",
@@ -70,6 +70,12 @@ static struct mcu_t {
        .timer0 = {
                .name = '0',
                .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
                .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
@@ -113,7 +119,7 @@ static void init(struct avr_t * avr)
 
        avr_eeprom_init(avr, &mcu->eeprom);
        avr_ioport_init(avr, &mcu->portb);
-       avr_timer8_init(avr, &mcu->timer0);
+       avr_timer_init(avr, &mcu->timer0);
 }
 
 static void reset(struct avr_t * avr)

diff --git a/simavr/cores/sim_tinyx5.c b/simavr/cores/sim_tinyx5.c
index ff72f78..8631021 100644 (file)
--- a/simavr/cores/sim_tinyx5.c
+++ b/simavr/cores/sim_tinyx5.c
@@ -34,8 +34,9 @@ void tx5_init(struct avr_t * avr)
        avr_eeprom_init(avr, &mcu->eeprom);
        avr_extint_init(avr, &mcu->extint);
        avr_ioport_init(avr, &mcu->portb);
-       avr_timer8_init(avr, &mcu->timer0);
-       avr_timer8_init(avr, &mcu->timer1);
+       avr_adc_init(avr, &mcu->adc);
+       avr_timer_init(avr, &mcu->timer0);
+       avr_timer_init(avr, &mcu->timer1);
 }
 
 void tx5_reset(struct avr_t * avr)

diff --git a/simavr/cores/sim_tinyx5.h b/simavr/cores/sim_tinyx5.h
index 3b7f760..8d42268 100644 (file)
--- a/simavr/cores/sim_tinyx5.h
+++ b/simavr/cores/sim_tinyx5.h
@@ -28,7 +28,8 @@
 #include "avr_eeprom.h"
 #include "avr_extint.h"
 #include "avr_ioport.h"
-#include "avr_timer8.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
 
 void tx5_init(struct avr_t * avr);
 void tx5_reset(struct avr_t * avr);
@@ -41,7 +42,8 @@ struct mcu_t {
        avr_eeprom_t    eeprom;
        avr_extint_t    extint;
        avr_ioport_t    portb;
-       avr_timer8_t    timer0, timer1;
+       avr_adc_t               adc;
+       avr_timer_t     timer0, timer1;
 };
 
 #ifdef SIM_CORENAME
@@ -63,16 +65,7 @@ struct mcu_t SIM_CORENAME = {
        },
        AVR_EEPROM_DECLARE(EE_RDY_vect),
        .extint = {
-               .eint[0] = {
-                       .port_ioctl = AVR_IOCTL_IOPORT_GETIRQ('B'),
-                       .port_pin = PB2,
-                       .isc = { AVR_IO_REGBIT(MCUCR, ISC00), AVR_IO_REGBIT(MCUCR, ISC01) },
-                       .vector = {
-                               .enable = AVR_IO_REGBIT(GIMSK, INT0),
-                               .raised = AVR_IO_REGBIT(GIFR, INTF0),
-                               .vector = INT0_vect,
-                       },
-               }
+               AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
        },
        .portb = {
                .name = 'B',  .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
@@ -83,9 +76,41 @@ struct mcu_t SIM_CORENAME = {
                },
                .r_pcint = PCMSK,
        },
+       .adc = {
+               .r_admux = ADMUX,
+               .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
+                                       AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
+               .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), AVR_IO_REGBIT(ADMUX, REFS2), },
+               .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
+               .r_adcsra = ADCSRA,
+               .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
+               .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
+               .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
+               .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
+
+               .r_adch = ADCH,
+               .r_adcl = ADCL,
+
+               .r_adcsrb = ADCSRB,
+               .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+               .bin = AVR_IO_REGBIT(ADCSRB, BIN),
+               .ipr = AVR_IO_REGBIT(ADCSRA, IPR),
+
+               .adc = {
+                       .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
+                       .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
+                       .vector = ADC_vect,
+               },
+       },
        .timer0 = {
                .name = '0',
                .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       [2] = AVR_TIMER_WGM_CTC(),
+                       [3] = AVR_TIMER_WGM_FASTPWM(),
+                       [7] = AVR_TIMER_WGM_FASTPWM(),
+               },
                .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 

diff --git a/simavr/sim/avr_extint.h b/simavr/sim/avr_extint.h
index c05a7eb..8b0f1ba 100644 (file)
--- a/simavr/sim/avr_extint.h
+++ b/simavr/sim/avr_extint.h
@@ -28,8 +28,8 @@
 
 
 enum {
-       EXTINT_IRQ_INT0 = 0,
-       EXTINT_IRQ_INT1, EXTINT_IRQ_INT2, EXTINT_IRQ_INT3,
+       EXTINT_IRQ_OUT_INT0 = 0,
+       EXTINT_IRQ_OUT_INT1, EXTINT_IRQ_OUT_INT2, EXTINT_IRQ_OUT_INT3,
        EXTINT_COUNT
 };
 
@@ -72,4 +72,16 @@ void avr_extint_init(avr_t * avr, avr_extint_t * p);
                        },\
                }
 
+#define AVR_EXTINT_TINY_DECLARE(_index, _portname, _portpin, _IFR) \
+               .eint[_index] = { \
+                       .port_ioctl = AVR_IOCTL_IOPORT_GETIRQ(_portname), \
+                       .port_pin = _portpin, \
+                       .isc = { AVR_IO_REGBIT(MCUCR, ISC##_index##0), AVR_IO_REGBIT(MCUCR, ISC##_index##1) }, \
+                       .vector = { \
+                               .enable = AVR_IO_REGBIT(GIMSK, INT##_index), \
+                               .raised = AVR_IO_REGBIT(_IFR, INTF##_index), \
+                               .vector = INT##_index##_vect, \
+                       }, \
+               }
+
 #endif /* AVR_EXTINT_H_ */