first version of dac output and some test signals

diff --git a/vhdl/dac.qpf b/vhdl/dac.qpf
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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
+# Date created = 16:00:50  June 12, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "11.0"
+DATE = "16:00:50  June 12, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "3064at44"

diff --git a/vhdl/dac.vhd b/vhdl/dac.vhd
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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.std_logic_unsigned.all;
+
+entity dac is
+    Port ( clk : in STD_LOGIC;
+               dac_a : out  STD_LOGIC_VECTOR (4 downto 0);
+           dac_b : out  STD_LOGIC_VECTOR (4 downto 0);
+
+          test_port : out  STD_LOGIC_VECTOR (14 downto 0));
+end dac;
+
+
+architecture RTL of dac is
+signal counter : STD_LOGIC_VECTOR (20 downto 0);
+begin
+  test: process (clk) is
+  begin
+    if (rising_edge(clk)) then
+      counter <= counter + '1';
+
+               -- 5 bit R2R DAC 0-3.3V
+      dac_a <= counter (4 downto 0);
+      dac_b <= counter (9 downto 5);
+
+               -- other pins without assigment
+--      test_port <= counter (14 downto 0); -- four ports so that
+
+--      test_port_d <= counter (20 downto 13); -- all pins are tested
+--        test_pin <= counter (0);              -- test single bit left over
+    end if;
+  end process test;
+end RTL;
+