Spectrum analyzer shellcode, forked from Ossmann's. GPL polluted for now, but as...

git-svn-id: https://svn.code.sf.net/p/goodfet/code/trunk@1013 12e2690d-a6be-4b82-a7b7-67c4a43b65c8

diff --git a/shellcode/chipcon/cc1110/Makefile b/shellcode/chipcon/cc1110/Makefile
index 3430167..ec5cceb 100644 (file)
--- a/shellcode/chipcon/cc1110/Makefile
+++ b/shellcode/chipcon/cc1110/Makefile
@@ -8,7 +8,7 @@
 # Use lower RAM if needed.
 
 CC=sdcc --code-loc 0xF000 
-objs=crystal.ihx txpacket.ihx rxpacket.ihx txrxpacket.ihx reflex.ihx rxpacketp25.ihx reflexframe.ihx carrier.ihx
+objs=crystal.ihx txpacket.ihx rxpacket.ihx txrxpacket.ihx reflex.ihx rxpacketp25.ihx reflexframe.ihx carrier.ihx specan.ihx
 
 all: $(objs)
 

diff --git a/shellcode/chipcon/cc1110/ioCCxx10_bitdef.h b/shellcode/chipcon/cc1110/ioCCxx10_bitdef.h
new file mode 100644 (file)
index 0000000..7c84a0a
--- /dev/null
+++ b/shellcode/chipcon/cc1110/ioCCxx10_bitdef.h
@@ -0,0 +1,1284 @@
+/******************************************************************************\r
+    Filename: ioCCxx10_bitdef.h\r
+\r
+    This file contains the bit definitions of registers in CCxx10\r
+\r
+    Copyright 2008 Texas Instruments, Inc.\r
+******************************************************************************/\r
+#ifndef _IOCCXX10_BITDEF_H\r
+#define _IOCCXX10_BITDEF_H\r
+\r
+\r
+\r
+/* SEE DATA SHEET FOR DETAILS ABOUT THE FOLLOWING BIT MASKS */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Memory Control Registers\r
+ */\r
+\r
+// MPAGE (0x93) - Memory Page Select\r
+\r
+// MEMCTR (0xC7) - Memory Arbiter Control\r
+#define MEMCTR_CACHD                      0x02\r
+#define MEMCTR_PREFD                      0x01\r
+\r
+\r
+/*******************************************************************************\r
+ * CPU Registers\r
+ */\r
+\r
+// DPH0 (0x83) - Data Pointer 0 High Byte\r
+\r
+// DPL0 (0x82) - Data Pointer 0 Low Byte\r
+\r
+// DPH1 (0x85) - Data Pointer 1 High Byte\r
+\r
+// DPL1 (0x84) - Data Pointer 1 Low Byte\r
+\r
+// DPS (0x92) - Data Pointer Select\r
+#define DPS_VDPS                          0x01\r
+\r
+\r
+// PSW (0xD0) - Progrttus Word - bit accessible SFR register\r
+\r
+// ACC (0xE0) - Accumulator - bit accessible SFR register\r
+\r
+// B (0xF0) - B Register - bit accessible SFR register\r
+\r
+// SP (0x81) - Stack Pointer\r
+\r
+\r
+/*******************************************************************************\r
+ * Interrupt Control Registers\r
+ */\r
+\r
+// IEN0 (0xA8) - Interrupt Enable 0 Register - bit accessible SFR register\r
+\r
+// IEN1 (0xB8) - Interrupt Enable 1 Register - bit accessible SFR register\r
+\r
+// IEN2 (0x9A) - Interrupt Enable 2 Register\r
+#define IEN2_WDTIE                        0x20\r
+#define IEN2_P1IE                         0x10\r
+#define IEN2_UTX1IE                       0x08\r
+#define IEN2_I2STXIE                      0x08\r
+#define IEN2_UTX0IE                       0x04\r
+#define IEN2_P2IE                         0x02\r
+#define IEN2_USBIE                        0x02\r
+#define IEN2_RFIE                         0x01\r
+\r
+\r
+// TCON (0x88) - CPU Interrupt Flag 1 - bit accessible SFR register\r
+\r
+// S0CON (0x98) - CPU Interrupt Flag 2 - bit accessible SFR register\r
+\r
+// S1CON (0x9B) - CPU Interrupt Flag 3\r
+#define S1CON_RFIF_1                      0x02\r
+#define S1CON_RFIF_0                      0x01\r
+\r
+\r
+// IRCON (0xC0) - CPU Interrupt Flag 4 - bit accessible SFR register\r
+\r
+// IRCON2 (0xE8) - CPU Interrupt Flag 5 - bit accessible SFR register\r
+\r
+// IP1 (0xB9) - Interrupt Priority 1\r
+#define IP1_IPG5                          0x20\r
+#define IP1_IPG4                          0x10\r
+#define IP1_IPG3                          0x08\r
+#define IP1_IPG2                          0x04\r
+#define IP1_IPG1                          0x02\r
+#define IP1_IPG0                          0x01\r
+\r
+// IP0 (0xA9) - Interrupt Priority 0\r
+#define IP0_IPG5                          0x20\r
+#define IP0_IPG4                          0x10\r
+#define IP0_IPG3                          0x08\r
+#define IP0_IPG2                          0x04\r
+#define IP0_IPG1                          0x02\r
+#define IP0_IPG0                          0x01\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Power Management and Clocks\r
+ */\r
+\r
+// PCON (0x87) - Power Mode Control\r
+#define PCON_IDLE                         0x01\r
+\r
+\r
+// SLEEP (0xBE) - Sleep Mode Control\r
+#define SLEEP_USB_EN                      0x80\r
+#define SLEEP_XOSC_S                      0x40\r
+#define SLEEP_HFRC_S                      0x20\r
+#define SLEEP_RST                         0x18\r
+#define SLEEP_RST0                        0x08\r
+#define SLEEP_RST1                        0x10\r
+#define SLEEP_OSC_PD                      0x04\r
+#define SLEEP_MODE                        0x03\r
+#define SLEEP_MODE1                       0x02\r
+#define SLEEP_MODE0                       0x01\r
+\r
+#define SLEEP_RST_POR_BOD                 (0x00 << 3)\r
+#define SLEEP_RST_EXT                     (0x01 << 3)\r
+#define SLEEP_RST_WDT                     (0x02 << 3)\r
+\r
+#define SLEEP_MODE_PM0                    (0x00)\r
+#define SLEEP_MODE_PM1                    (0x01)\r
+#define SLEEP_MODE_PM2                    (0x02)\r
+#define SLEEP_MODE_PM3                    (0x03)\r
+\r
+\r
+// CLKCON (0xC6) - Clock Control\r
+#define CLKCON_OSC32                      0x80  // bit mask, for the slow 32k clock oscillator\r
+#define CLKCON_OSC                        0x40  // bit mask, for the system clock oscillator\r
+#define CLKCON_TICKSPD                    0x38  // bit mask, for timer ticks output setting\r
+#define CLKCON_TICKSPD0                   0x08  // bit mask, for timer ticks output setting\r
+#define CLKCON_TICKSPD1                   0x10  // bit mask, for timer ticks output setting\r
+#define CLKCON_TICKSPD2                   0x20  // bit mask, for timer ticks output setting\r
+#define CLKCON_CLKSPD                     0x07  // bit mask, for the clock speed\r
+#define CLKCON_CLKSPD0                    0x01  // bit mask, for the clock speed\r
+#define CLKCON_CLKSPD1                    0x02  // bit mask, for the clock speed\r
+#define CLKCON_CLKSPD2                    0x04  // bit mask, for the clock speed\r
+\r
+#define TICKSPD_DIV_1                     (0x00 << 3)\r
+#define TICKSPD_DIV_2                     (0x01 << 3)\r
+#define TICKSPD_DIV_4                     (0x02 << 3)\r
+#define TICKSPD_DIV_8                     (0x03 << 3)\r
+#define TICKSPD_DIV_16                    (0x04 << 3)\r
+#define TICKSPD_DIV_32                    (0x05 << 3)\r
+#define TICKSPD_DIV_64                    (0x06 << 3)\r
+#define TICKSPD_DIV_128                   (0x07 << 3)\r
+\r
+#define CLKSPD_DIV_1                      (0x00)\r
+#define CLKSPD_DIV_2                      (0x01)\r
+#define CLKSPD_DIV_4                      (0x02)\r
+#define CLKSPD_DIV_8                      (0x03)\r
+#define CLKSPD_DIV_16                     (0x04)\r
+#define CLKSPD_DIV_32                     (0x05)\r
+#define CLKSPD_DIV_64                     (0x06)\r
+#define CLKSPD_DIV_128                    (0x07)\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *  Flash Controller\r
+ */\r
+\r
+// FCTL (0xAE) - Flash Control\r
+#define FCTL_BUSY                         0x80\r
+#define FCTL_SWBSY                        0x40\r
+#define FCTL_CONTRD                       0x10\r
+#define FCTL_WRITE                        0x02\r
+#define FCTL_ERASE                        0x01\r
+\r
+\r
+// FWDATA (0xAF) - Flash Write Data\r
+\r
+// FADDRH (0xAD) - Flash Address High Byte\r
+\r
+// FADDRL (0xAC) - Flash Address Low Byte\r
+\r
+// FWT (0xAB) - Flash Write Timing (Only bit 0-5 R/W)\r
+\r
+\r
+/*******************************************************************************\r
+ * I/O Ports\r
+ */\r
+\r
+// P0 (0x80) - Port 0 - bit accessible SFR register\r
+\r
+// P1 (0x90) - Port 1 - bit accessible SFR register\r
+\r
+// P2 (0xA0) - Port 2 - bit accessible SFR register\r
+\r
+// PERCFG (0xF1) - Peripheral Control\r
+#define PERCFG_T1CFG                      0x40\r
+#define PERCFG_T3CFG                      0x20\r
+#define PERCFG_T4CFG                      0x10\r
+#define PERCFG_U1CFG                      0x02\r
+#define PERCFG_U0CFG                      0x01\r
+\r
+\r
+\r
+// ADCCFG (0xF2) - ADC input Configuration\r
+#define ADCCFG_7                          0x80\r
+#define ADCCFG_6                          0x40\r
+#define ADCCFG_5                          0x20\r
+#define ADCCFG_4                          0x10\r
+#define ADCCFG_3                          0x08\r
+#define ADCCFG_2                          0x04\r
+#define ADCCFG_1                          0x02\r
+#define ADCCFG_0                          0x01\r
+\r
+\r
+// P0SEL (0xF3) - Port 0 Function Select (bit 7 not used)\r
+\r
+// P1SEL (0xF4) - Port 1 Function Select\r
+\r
+// P2SEL (0xF5) - Port 2 Function Select\r
+#define P2SEL_PRI3P1                      0x40\r
+#define P2SEL_PRI2P1                      0x20\r
+#define P2SEL_PRI1P1                      0x10\r
+#define P2SEL_PRI0P1                      0x08\r
+#define P2SEL_SELP2_4                     0x04\r
+#define P2SEL_SELP2_3                     0x02\r
+#define P2SEL_SELP2_0                     0x01\r
+\r
+\r
+// P0DIR (0xFD) - Port 0 Direction Select\r
+\r
+// P1DIR (0xFE) - Port 1 Direction Select\r
+\r
+// P2DIR (0xFF) - Port 2 Direction\r
+#define P2DIR_PRIP0                       0xC0\r
+#define P2DIR_0PRIP0                      0x40\r
+#define P2DIR_1PRIP0                      0x80\r
+#define P2DIR_DIRP2                       0x1F\r
+\r
+#define P2DIR_PRIP0_0                     (0x00 << 6)\r
+#define P2DIR_PRIP0_1                     (0x01 << 6)\r
+#define P2DIR_PRIP0_2                     (0x02 << 6)\r
+#define P2DIR_PRIP0_3                     (0x03 << 6)\r
+\r
+#define P2DIR_DIRP2_4                     (0x10)\r
+#define P2DIR_DIRP2_3                     (0x08)\r
+#define P2DIR_DIRP2_2                     (0x04)\r
+#define P2DIR_DIRP2_1                     (0x02)\r
+#define P2DIR_DIRP2_0                     (0x01)\r
+\r
+\r
+\r
+// P0INP (0x8F) - Port 0 Input Mode (bit 0 & 1 not used)\r
+\r
+// P1INP (0xF6) - Port 1 Input Mode (bit 0 & 1 not used)\r
+\r
+// P2INP (0xF7) - Port 2 Input Mode\r
+#define P2INP_PDUP2                       0x80\r
+#define P2INP_PDUP1                       0x40\r
+#define P2INP_PDUP0                       0x20\r
+#define P2INP_MDP2                        0x1F\r
+\r
+#define P2INP_MDP2_0                      (0x01)\r
+#define P2INP_MDP2_1                      (0x02)\r
+#define P2INP_MDP2_2                      (0x04)\r
+#define P2INP_MDP2_3                      (0x08)\r
+#define P2INP_MDP2_4                      (0x10)\r
+\r
+\r
+\r
+// P0IFG (0x89) - Port 0 Interrupt Status Flag\r
+\r
+// P1IFG (0x8A) - Port 1 Interrupt Status Flag\r
+\r
+// P2IFG (0x8B) - Port 2 Interrupt Status Flag (bit 7 - 5 not used)\r
+\r
+// PICTL (0x8C) - Port Interrupt Control\r
+#define PICTL_PADSC                       0x40\r
+#define PICTL_P2IEN                       0x20\r
+#define PICTL_P0IENH                      0x10\r
+#define PICTL_P0IENL                      0x08\r
+#define PICTL_P2ICON                      0x04\r
+#define PICTL_P1ICON                      0x02\r
+#define PICTL_P0ICON                      0x01\r
+\r
+\r
+// P1IEN (0x8D) - Port 1 Interrupt Mask\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * DMA Controller\r
+ */\r
+\r
+// DMAARM (0xD6) - DMA Channel Arm\r
+#define DMAARM_ABORT                      0x80\r
+#define DMAARM4                           0x10\r
+#define DMAARM3                           0x08\r
+#define DMAARM2                           0x04\r
+#define DMAARM1                           0x02\r
+#define DMAARM0                           0x01\r
+\r
+\r
+// DMAREQ (0xD7) - DMA Channel Start Request and Status\r
+#define DMAREQ4                           0x10\r
+#define DMAREQ3                           0x08\r
+#define DMAREQ2                           0x04\r
+#define DMAREQ1                           0x02\r
+#define DMAREQ0                           0x01\r
+\r
+\r
+// DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte\r
+\r
+// DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte\r
+\r
+// DMA1CFGH (0xD3) - DMA Channel 1 - 4 Configuration Address High By\r
+\r
+// DMA1CFGL (0xD2) - DMA Channel 1 - 4 Configuration Address Low Byte\r
+\r
+// DMAIRQ (0xD1) - DMA Interrupt Flag\r
+#define DMAIRQ_DMAIF4                     0x10\r
+#define DMAIRQ_DMAIF3                     0x08\r
+#define DMAIRQ_DMAIF2                     0x04\r
+#define DMAIRQ_DMAIF1                     0x02\r
+#define DMAIRQ_DMAIF0                     0x01\r
+\r
+\r
+// T1CNTH (0xE3) - Timer 1 Counter High\r
+\r
+// T1CNTL (0xE2) - Timer 1 Counter Low\r
+\r
+// T1CTL (0xE4) - Timer 1 Control and Status\r
+#define T1CTL_CH2IF                       0x80 // Timer 1 channel 2 interrupt flag\r
+#define T1CTL_CH1IF                       0x40 // Timer 1 channel 1 interrupt flag\r
+#define T1CTL_CH0IF                       0x20 // Timer 1 channel 0 interrupt flag\r
+#define T1CTL_OVFIF                       0x10 // Timer 1 counter overflow interrupt flag\r
+#define T1CTL_DIV                         0x0C\r
+#define T1CTL_DIV0                        0x04\r
+#define T1CTL_DIV1                        0x08\r
+#define T1CTL_MODE                        0x03\r
+#define T1CTL_MODE0                       0x01\r
+#define T1CTL_MODE1                       0x02\r
+\r
+#define T1CTL_DIV_1                       (0x00 << 2) // Divide tick frequency by 1\r
+#define T1CTL_DIV_8                       (0x01 << 2) // Divide tick frequency by 8\r
+#define T1CTL_DIV_32                      (0x02 << 2) // Divide tick frequency by 32\r
+#define T1CTL_DIV_128                     (0x03 << 2) // Divide tick frequency by 128\r
+\r
+#define T1CTL_MODE_SUSPEND                (0x00)    // Operation is suspended (halt)\r
+#define T1CTL_MODE_FREERUN                (0x01)    // Free Running mode\r
+#define T1CTL_MODE_MODULO                 (0x02)    // Modulo\r
+#define T1CTL_MODE_UPDOWN                 (0x03)    // Up/down\r
+\r
+\r
+// T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control\r
+#define T1CCTL0_CPSEL                     0x80    // Timer 1 channel 0 capture select\r
+#define T1CCTL0_IM                        0x40    // Channel 0 Interrupt mask\r
+#define T1CCTL0_CMP                       0x38\r
+#define T1CCTL0_CMP0                      0x08\r
+#define T1CCTL0_CMP1                      0x10\r
+#define T1CCTL0_CMP2                      0x20\r
+#define T1CCTL0_MODE                      0x04    // Capture or compare mode\r
+#define T1CCTL0_CAP                       0x03\r
+#define T1CCTL0_CAP0                      0x01\r
+#define T1CCTL0_CAP1                      0x02\r
+\r
+#define T1C0_SET_ON_CMP                   (0x00 << 3)    // Clear output on compare-up set on 0\r
+#define T1C0_CLR_ON_CMP                   (0x01 << 3)    // Set output on compare-up clear on 0\r
+#define T1C0_TOG_ON_CMP                   (0x02 << 3)    // Toggle output on compare\r
+#define T1C0_SET_CMP_UP_CLR_0             (0x03 << 3)    // Clear output on compare\r
+#define T1C0_CLR_CMP_UP_SET_0             (0x04 << 3)    // Set output on compare\r
+\r
+#define T1C0_NO_CAP                       (0x00)    // No capture\r
+#define T1C0_RISE_EDGE                    (0x01)    // Capture on rising edge\r
+#define T1C0_FALL_EDGE                    (0x02)    // Capture on falling edge\r
+#define T1C0_BOTH_EDGE                    (0x03)    // Capture on both edges\r
+\r
+\r
+// T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High\r
+\r
+// T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low\r
+\r
+// T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control\r
+#define T1CCTL1_CPSEL                     0x80    // Timer 1 channel 1 capture select\r
+#define T1CCTL1_IM                        0x40    // Channel 1 Interrupt mask\r
+#define T1CCTL1_CMP                       0x38\r
+#define T1CCTL1_CMP0                      0x08\r
+#define T1CCTL1_CMP1                      0x10\r
+#define T1CCTL1_CMP2                      0x20\r
+#define T1CCTL1_MODE                      0x04    // Capture or compare mode\r
+#define T1CCTL1_DSM_SPD                   0x04\r
+#define T1CCTL1_CAP                       0x03\r
+#define T1CCTL1_CAP0                      0x01\r
+#define T1CCTL1_CAP1                      0x02\r
+\r
+#define T1C1_SET_ON_CMP                   (0x00 << 3)  // Set output on compare\r
+#define T1C1_CLR_ON_CMP                   (0x01 << 3)  // Clear output on compare\r
+#define T1C1_TOG_ON_CMP                   (0x02 << 3)  // Toggle output on compare\r
+#define T1C1_SET_CMP_UP_CLR_0             (0x03 << 3)  // Set output on compare-up clear on 0\r
+#define T1C1_CLR_CMP_UP_SET_0             (0x04 << 3)  // Clear output on compare-up set on 0\r
+#define T1C1_SET_C1_CLR_C0                (0x05 << 3)  // Set when equal to T1CC1, clear when equal to T1CC0\r
+#define T1C1_CLR_C1_SET_C0                (0x06 << 3)  // Clear when equal to T1CC1, set when equal to T1CC0\r
+#define T1C1_DSM_MODE                     (0x07 << 3)  // DSM mode\r
+\r
+#define T1C1_NO_CAP                       (0x00)     // No capture\r
+#define T1C1_RISE_EDGE                    (0x01)    // Capture on rising edge\r
+#define T1C1_FALL_EDGE                    (0x02)    // Capture on falling edge\r
+#define T1C1_BOTH_EDGE                    (0x03)    // Capture on both edges\r
+\r
+#define DSM_IP_ON_OS_ON                   (0x00)    // Interpolator & output shaping enabled\r
+#define DSM_IP_ON_OS_OFF                  (0x01)    // Interpolator enabled & output shaping disabled\r
+#define DSM_IP_OFF_OS_ON                  (0x02)    // Interpolator disabled & output shaping enabled\r
+#define DSM_IP_OFF_OS_OFF                 (0x03)    // Interpolator & output shaping disabled\r
+\r
+\r
+\r
+// T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High\r
+\r
+// T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low\r
+\r
+// T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control\r
+#define T1CCTL2_CPSEL                     0x80    // Timer 1 channel 2 capture select\r
+#define T1CCTL2_IM                        0x40    // Channel 2 Interrupt mask\r
+#define T1CCTL2_CMP                       0x38\r
+#define T1CCTL2_CMP0                      0x08\r
+#define T1CCTL2_CMP1                      0x10\r
+#define T1CCTL2_CMP2                      0x20\r
+#define T1CCTL2_MODE                      0x04    // Capture or compare mode\r
+#define T1CCTL2_CAP                       0x03\r
+#define T1CCTL2_CAP0                      0x01\r
+#define T1CCTL2_CAP1                      0x02\r
+\r
+#define T1C2_SET_ON_CMP                   (0x00 << 3)  // Set output on compare\r
+#define T1C2_CLR_ON_CMP                   (0x01 << 3)  // Clear output on compare\r
+#define T1C2_TOG_ON_CMP                   (0x02 << 3)  // Toggle output on compare\r
+#define T1C2_SET_CMP_UP_CLR_0             (0x03 << 3)  // Set output on compare-up clear on 0\r
+#define T1C2_CLR_CMP_UP_SET_0             (0x04 << 3)  // Clear output on compare-up set on 0\r
+#define T1C2_SET_C2_CLR_C0                (0x05 << 3)  // Set when equal to T1CC2, clear when equal to T1CC0\r
+#define T1C2_CLR_C2_SET_C0                (0x06 << 3)  // Clear when equal to T1CC2, set when equal to T1CC0\r
+\r
+#define T1C2_NO_CAP                       (0x00)     // No capture\r
+#define T1C2_RISE_EDGE                    (0x01)    // Capture on rising edge\r
+#define T1C2_FALL_EDGE                    (0x02)    // Capture on falling edge\r
+#define T1C2_BOTH_EDGE                    (0x03)    // Capture on both edges\r
+\r
+\r
+// T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High\r
+\r
+// T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low\r
+\r
+// T2CTL (0x9E) - Timer 2 Control\r
+#define T2CTL_TEX                         0x40\r
+#define T2CTL_INT                         0x10    // Enable Timer 2 interrupt\r
+#define T2CTL_TIG                         0x04    // Tick generator mode\r
+#define T2CTL_TIP                         0x03\r
+#define T2CTL_TIP0                        0x01\r
+#define T2CTL_TIP1                        0x02\r
+\r
+#define T2CTL_TIP_64                      (0x00)\r
+#define T2CTL_TIP_128                     (0x01)\r
+#define T2CTL_TIP_256                     (0x02)\r
+#define T2CTL_TIP_1024                    (0x03)\r
+\r
+\r
+// T2CT (0x9C) - Timer 2 Count\r
+\r
+// T2PR (0x9D) - Timer 2 Prescaler\r
+\r
+// WORTIME0 (0xA5) - Sleep Timer Low Byte\r
+\r
+// WORTIME1 (0xA6) - Sleep Timer High Byte\r
+\r
+// WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High\r
+\r
+// WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low\r
+\r
+// WORCTL (0xA2) - Sleep Timer Control\r
+#define WORCTL_WOR_RESET                  0x04\r
+#define WORCTL_WOR_RES                    0x03\r
+#define WORCTL_WOR_RES0                   0x01\r
+#define WORCTL_WOR_RES1                   0x02\r
+\r
+#define WORCTL_WOR_RES_1                  (0x00)\r
+#define WORCTL_WOR_RES_32                 (0x01)\r
+#define WORCTL_WOR_RES_1024               (0x02)\r
+#define WORCTL_WOR_RES_32768              (0x03)\r
+\r
+\r
+// WORIRQ (0xA1) - Sleep Timer Interrupt Control\r
+#define WORIRQ_EVENT0_MASK                0x10\r
+#define WORIRQ_EVENT0_FLAG                0x01\r
+\r
+\r
+// T3CNT (0xCA) - Timer 3 Counter\r
+\r
+// T3CTL (0xCB) - Timer 3 Control\r
+#define T3CTL_DIV                         0xE0\r
+#define T3CTL_DIV0                        0x20\r
+#define T3CTL_DIV1                        0x40\r
+#define T3CTL_DIV2                        0x80\r
+#define T3CTL_START                       0x10\r
+#define T3CTL_OVFIM                       0x08\r
+#define T3CTL_CLR                         0x04\r
+#define T3CTL_MODE                        0x03\r
+#define T3CTL_MODE0                       0x01\r
+#define T3CTL_MODE1                       0x02\r
+\r
+#define T3CTL_DIV_1                       (0x00 << 5)\r
+#define T3CTL_DIV_2                       (0x01 << 5)\r
+#define T3CTL_DIV_4                       (0x02 << 5)\r
+#define T3CTL_DIV_8                       (0x03 << 5)\r
+#define T3CTL_DIV_16                      (0x04 << 5)\r
+#define T3CTL_DIV_32                      (0x05 << 5)\r
+#define T3CTL_DIV_64                      (0x06 << 5)\r
+#define T3CTL_DIV_128                     (0x07 << 5)\r
+\r
+#define T3CTL_MODE_FREERUN                (0x00)\r
+#define T3CTL_MODE_DOWN                   (0x01)\r
+#define T3CTL_MODE_MODULO                 (0x02)\r
+#define T3CTL_MODE_UPDOWN                 (0x03)\r
+\r
+\r
+\r
+// T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control\r
+#define T3CCTL0_IM                        0x40\r
+#define T3CCTL0_MODE                      0x04\r
+#define T3CCTL0_CMP                       0x38\r
+#define T3CCTL0_CMP0                      0x08\r
+#define T3CCTL0_CMP1                      0x10\r
+#define T3CCTL0_CMP2                      0x20\r
+\r
+#define T3C0_SET_ON_CMP                   (0x00 << 3)  // Set output on compare\r
+#define T3C0_CLR_ON_CMP                   (0x01 << 3)  // Clear output on compare\r
+#define T3C0_TOG_ON_CMP                   (0x02 << 3)  // Toggle output on compare\r
+#define T3C0_SET_CMP_UP_CLR_0             (0x03 << 3)  // Set output on compare-up clear on 0\r
+#define T3C0_CLR_CMP_UP_SET_0             (0x04 << 3)  // Clear output on compare-up set on 0\r
+#define T3C0_SET_CMP_CLR_255              (0x05 << 3)  // Set when equal to T3CC0, clear on 255\r
+#define T3C0_CLR_CMP_SET_0                (0x06 << 3)  // Clear when equal to T3CC0, set on 0\r
+\r
+\r
+\r
+// T3CC0 (0xCD) - Timer 3 Channel 0 Compare Value\r
+\r
+// T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control\r
+\r
+#define T3CCTL1_IM                        0x40\r
+#define T3CCTL1_MODE                      0x04\r
+#define T3CCTL1_CMP                       0x38\r
+#define T3CCTL1_CMP0                      0x08\r
+#define T3CCTL1_CMP1                      0x10\r
+#define T3CCTL1_CMP2                      0x20\r
+\r
+#define T3C1_SET_ON_CMP                   (0x00 << 3)  // Set output on compare\r
+#define T3C1_CLR_ON_CMP                   (0x01 << 3)  // Clear output on compare\r
+#define T3C1_TOG_ON_CMP                   (0x02 << 3)  // Toggle output on compare\r
+#define T3C1_SET_CMP_UP_CLR_0             (0x03 << 3)  // Set output on compare-up clear on 0\r
+#define T3C1_CLR_CMP_UP_SET_0             (0x04 << 3)  // Clear output on compare-up set on 0\r
+#define T3C1_SET_CMP_CLR_C0               (0x05 << 3)  // Set when equal to T3CC1, clear when equal to T3CC0\r
+#define T3C1_CLR_CMP_SET_C0               (0x06 << 3)  // Clear when equal to T3CC1, set when equal to T3CC0\r
+\r
+\r
+// T3CC1 (0xCF) - Timer 3 Channel 1 Compare Value\r
+\r
+// T4CNT (0xEA) - Timer 4 Counter\r
+\r
+// T4CTL (0xEB) - Timer 4 Control\r
+#define T4CTL_DIV                         0xE0\r
+#define T4CTL_DIV0                        0x20\r
+#define T4CTL_DIV1                        0x40\r
+#define T4CTL_DIV2                        0x80\r
+#define T4CTL_START                       0x10\r
+#define T4CTL_OVFIM                       0x08\r
+#define T4CTL_CLR                         0x04\r
+#define T4CTL_MODE                        0x03\r
+#define T4CTL_MODE0                       0x01\r
+#define T4CTL_MODE1                       0x02\r
+\r
+#define T4CTL_MODE_FREERUN                (0x00)\r
+#define T4CTL_MODE_DOWN                   (0x01)\r
+#define T4CTL_MODE_MODULO                 (0x02)\r
+#define T4CTL_MODE_UPDOWN                 (0x03)\r
+\r
+#define T4CTL_DIV_1                       (0x00 << 5)\r
+#define T4CTL_DIV_2                       (0x01 << 5)\r
+#define T4CTL_DIV_4                       (0x02 << 5)\r
+#define T4CTL_DIV_8                       (0x03 << 5)\r
+#define T4CTL_DIV_16                      (0x04 << 5)\r
+#define T4CTL_DIV_32                      (0x05 << 5)\r
+#define T4CTL_DIV_64                      (0x06 << 5)\r
+#define T4CTL_DIV_128                     (0x07 << 5)\r
+\r
+\r
+// T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control\r
+#define T4CCTL0_IM                        0x40\r
+#define T4CCTL0_CMP                       0x38\r
+#define T4CCTL0_CMP0                      0x08\r
+#define T4CCTL0_CMP1                      0x10\r
+#define T4CCTL0_CMP2                      0x20\r
+#define T4CCTL0_MODE                      0x04\r
+\r
+#define T4CCTL0_SET_ON_CMP                (0x00 << 3)\r
+#define T4CCTL0_CLR_ON_CMP                (0x01 << 3)\r
+#define T4CCTL0_TOG_ON_CMP                (0x02 << 3)\r
+#define T4CCTL0_SET_CMP_UP_CLR_0          (0x03 << 3)\r
+#define T4CCTL0_CLR_CMP_UP_SET_0          (0x04 << 3)\r
+#define T4CCTL0_SET_CMP_CLR_255           (0x05 << 3)\r
+#define T4CCTL0_CLR_CMP_SET_0             (0x06 << 3)\r
+\r
+\r
+// T4CC0 (0xED) - Timer 4 Channel 0 Compare Value\r
+\r
+// T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control\r
+#define T4CCTL1_IM                        0x40\r
+#define T4CCTL1_CMP                       0x38\r
+#define T4CCTL1_CMP0                      0x08\r
+#define T4CCTL1_CMP1                      0x10\r
+#define T4CCTL1_CMP2                      0x20\r
+#define T4CCTL1_MODE                      0x04\r
+\r
+#define T4CCTL1_SET_ON_CMP                (0x00 << 3)\r
+#define T4CCTL1_CLR_ON_CMP                (0x01 << 3)\r
+#define T4CCTL1_TOG_ON_CMP                (0x02 << 3)\r
+#define T4CCTL1_SET_CMP_UP_CLR_0          (0x03 << 3)\r
+#define T4CCTL1_CLR_CMP_UP_SET_0          (0x04 << 3)\r
+#define T4CCTL1_SET_CMP_CLR_C0            (0x05 << 3)\r
+#define T4CCTL1_CLR_CMP_SET_C0            (0x06 << 3)\r
+\r
+\r
+// TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag - bit accessible SFR register\r
+\r
+\r
+/*******************************************************************************\r
+ * ADC\r
+ */\r
+\r
+// ADCL (0xBA) - ADC Data Low (only bit 7-4 used)\r
+\r
+// ADCH (0xBB) - ADC Data High\r
+\r
+// ADCCON1 (0xB4) - ADC Control 1\r
+#define ADCCON1_EOC                       0x80\r
+#define ADCCON1_ST                        0x40\r
+#define ADCCON1_STSEL                     0x30\r
+#define ADCCON1_STSEL0                    0x10\r
+#define ADCCON1_STSEL1                    0x20\r
+#define ADCCON1_RCTRL                     0x0C\r
+#define ADCCON1_RCTRL0                    0x04\r
+#define ADCCON1_RCTRL1                    0x08\r
+\r
+#define STSEL_P2_0                        (0x00 << 4)\r
+#define STSEL_FULL_SPEED                  (0x01 << 4)\r
+#define STSEL_T1C0_CMP_EVT                (0x02 << 4)\r
+#define STSEL_ST                          (0x03 << 4)\r
+\r
+#define ADCCON1_RCTRL_COMPL               (0x00 << 2)\r
+#define ADCCON1_RCTRL_LFSR13              (0x01 << 2)\r
+\r
+\r
+\r
+// ADCCON2 (0xB5) - ADC Control 2\r
+#define ADCCON2_SREF                      0xC0\r
+#define ADCCON2_SREF0                     0x40\r
+#define ADCCON2_SREF1                     0x80\r
+#define ADCCON2_SDIV                      0x30\r
+#define ADCCON2_SDIV0                     0x10\r
+#define ADCCON2_SDIV1                     0x20\r
+#define ADCCON2_SCH                       0x0F\r
+#define ADCCON2_SCH0                      0x01\r
+#define ADCCON2_SCH1                      0x02\r
+#define ADCCON2_SCH2                      0x04\r
+#define ADCCON2_SCH3                      0x08\r
+\r
+#define ADCCON2_SREF_1_25V                (0x00 << 6)\r
+#define ADCCON2_SREF_P0_7                 (0x01 << 6)\r
+#define ADCCON2_SREF_AVDD                 (0x02 << 6)\r
+#define ADCCON2_SREF_P0_6_P0_7            (0x03 << 6)\r
+\r
+#define ADCCON2_SDIV_64                   (0x00 << 4)\r
+#define ADCCON2_SDIV_128                  (0x01 << 4)\r
+#define ADCCON2_SDIV_256                  (0x02 << 4)\r
+#define ADCCON2_SDIV_512                  (0x03 << 4)\r
+\r
+#define ADCCON2_SCH_AIN0                  (0x00)\r
+#define ADCCON2_SCH_AIN1                  (0x01)\r
+#define ADCCON2_SCH_AIN2                  (0x02)\r
+#define ADCCON2_SCH_AIN3                  (0x03)\r
+#define ADCCON2_SCH_AIN4                  (0x04)\r
+#define ADCCON2_SCH_AIN5                  (0x05)\r
+#define ADCCON2_SCH_AIN6                  (0x06)\r
+#define ADCCON2_SCH_AIN7                  (0x07)\r
+#define ADCCON2_SCH_AIN0_1                (0x08)\r
+#define ADCCON2_SCH_AIN2_3                (0x09)\r
+#define ADCCON2_SCH_AIN4_5                (0x0A)\r
+#define ADCCON2_SCH_AIN6_7                (0x0B)\r
+#define ADCCON2_SCH_GND                   (0x0C)\r
+#define ADCCON2_SCH_POSVOL                (0x0D)\r
+#define ADCCON2_SCH_TEMPR                 (0x0E)\r
+#define ADCCON2_SCH_VDD_3                 (0x0F)\r
+\r
+\r
+// ADCCON3 (0xB6) - ADC Control 3\r
+#define ADCCON3_EREF                      0xC0\r
+#define ADCCON3_EREF0                     0x40\r
+#define ADCCON3_EREF1                     0x80\r
+#define ADCCON3_EDIV                      0x30\r
+#define ADCCON3_EDIV0                     0x10\r
+#define ADCCON3_EDIV1                     0x20\r
+#define ADCCON2_ECH                       0x0F\r
+#define ADCCON2_ECH0                      0x01\r
+#define ADCCON2_ECH1                      0x02\r
+#define ADCCON2_ECH2                      0x04\r
+#define ADCCON2_ECH3                      0x08\r
+\r
+#define ADCCON3_EREF_1_25V                (0x00 << 6)\r
+#define ADCCON3_EREF_P0_7                 (0x01 << 6)\r
+#define ADCCON3_EREF_AVDD                 (0x02 << 6)\r
+#define ADCCON3_EREF_P0_6_P0_7            (0x03 << 6)\r
+\r
+#define ADCCON3_EDIV_64                   (0x00 << 4)\r
+#define ADCCON3_EDIV_128                  (0x01 << 4)\r
+#define ADCCON3_EDIV_256                  (0x02 << 4)\r
+#define ADCCON3_EDIV_512                  (0x03 << 4)\r
+\r
+#define ADCCON3_ECH_AIN0                  (0x00)\r
+#define ADCCON3_ECH_AIN1                  (0x01)\r
+#define ADCCON3_ECH_AIN2                  (0x02)\r
+#define ADCCON3_ECH_AIN3                  (0x03)\r
+#define ADCCON3_ECH_AIN4                  (0x04)\r
+#define ADCCON3_ECH_AIN5                  (0x05)\r
+#define ADCCON3_ECH_AIN6                  (0x06)\r
+#define ADCCON3_ECH_AIN7                  (0x07)\r
+#define ADCCON3_ECH_AIN0_1                (0x08)\r
+#define ADCCON3_ECH_AIN2_3                (0x09)\r
+#define ADCCON3_ECH_AIN4_5                (0x0A)\r
+#define ADCCON3_ECH_AIN6_7                (0x0B)\r
+#define ADCCON3_ECH_GND                   (0x0C)\r
+#define ADCCON3_ECH_POSVOL                (0x0D)\r
+#define ADCCON3_ECH_TEMPR                 (0x0E)\r
+#define ADCCON3_ECH_VDD_3                 (0x0F)\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Random Number Generator\r
+ */\r
+\r
+// RNDL (0xBC) - Random Number Generator Data Low Byte\r
+\r
+// RNDH (0xBD) - Random Number Generator Data High Byte\r
+\r
+\r
+/*******************************************************************************\r
+ * AES\r
+ */\r
+\r
+// ENCCS (0xB3) - Encryption Control and Status\r
+#define ENCCS_MODE                        0x70\r
+#define ENCCS_MODE0                       0x10\r
+#define ENCCS_MODE1                       0x20\r
+#define ENCCS_MODE2                       0x40\r
+#define ENCCS_RDY                         0x08\r
+#define ENCCS_CMD                         0x06\r
+#define ENCCS_CMD0                        0x02\r
+#define ENCCS_CMD1                        0x04\r
+#define ENCCS_ST                          0x01\r
+\r
+#define ENCCS_MODE_CBC                    (0x00 << 4)\r
+#define ENCCS_MODE_CFB                    (0x01 << 4)\r
+#define ENCCS_MODE_OFB                    (0x02 << 4)\r
+#define ENCCS_MODE_CTR                    (0x03 << 4)\r
+#define ENCCS_MODE_ECB                    (0x04 << 4)\r
+#define ENCCS_MODE_CBCMAC                 (0x05 << 4)\r
+\r
+#define ENCCS_CMD_ENC                     (0x00 << 1)\r
+#define ENCCS_CMD_DEC                     (0x01 << 1)\r
+#define ENCCS_CMD_LDKEY                   (0x02 << 1)\r
+#define ENCCS_CMD_LDIV                    (0x03 << 1)\r
+\r
+\r
+// ENCDI (0xB1) - Encryption Input Data\r
+\r
+// ENCDO (0xB2) - Encryption Output Data\r
+\r
+\r
+/*******************************************************************************\r
+ * Watchdog Timer\r
+ */\r
+\r
+// WDCTL (0xC9) - Watchdog Timer Control\r
+#define WDCTL_CLR                         0xF0\r
+#define WDCTL_CLR0                        0x10\r
+#define WDCTL_CLR1                        0x20\r
+#define WDCTL_CLR2                        0x40\r
+#define WDCTL_CLR3                        0x80\r
+#define WDCTL_EN                          0x08\r
+#define WDCTL_MODE                        0x04\r
+#define WDCTL_INT                         0x03\r
+#define WDCTL_INT0                        0x01\r
+#define WDCTL_INT1                        0x02\r
+\r
+\r
+#define WDCTL_INT_SEC_1                   (0x00)\r
+#define WDCTL_INT1_MSEC_250               (0x01)\r
+#define WDCTL_INT2_MSEC_15                (0x02)\r
+#define WDCTL_INT3_MSEC_2                 (0x03)\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * USART\r
+ */\r
+\r
+// U0CSR (0x86) - USART 0 Control and Status\r
+\r
+#define U0CSR_MODE                        0x80\r
+#define U0CSR_RE                          0x40\r
+#define U0CSR_SLAVE                       0x20\r
+#define U0CSR_FE                          0x10\r
+#define U0CSR_ERR                         0x08\r
+#define U0CSR_RX_BYTE                     0x04\r
+#define U0CSR_TX_BYTE                     0x02\r
+#define U0CSR_ACTIVE                      0x01\r
+\r
+\r
+// U0UCR (0xC4) - USART 0 UART Control\r
+#define U0UCR_FLUSH                       0x80\r
+#define U0UCR_FLOW                        0x40\r
+#define U0UCR_D9                          0x20\r
+#define U0UCR_BIT9                        0x10\r
+#define U0UCR_PARITY                      0x08\r
+#define U0UCR_SPB                         0x04\r
+#define U0UCR_STOP                        0x02\r
+#define U0UCR_START                       0x01\r
+\r
+\r
+// U0GCR (0xC5) - USART 0 Generic Control\r
+#define U0GCR_CPOL                        0x80\r
+#define U0GCR_CPHA                        0x40\r
+#define U0GCR_ORDER                       0x20\r
+#define U0GCR_BAUD_E                      0x1F\r
+#define U0GCR_BAUD_E0                     0x01\r
+#define U0GCR_BAUD_E1                     0x02\r
+#define U0GCR_BAUD_E2                     0x04\r
+#define U0GCR_BAUD_E3                     0x08\r
+#define U0GCR_BAUD_E4                     0x10\r
+\r
+\r
+// U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer\r
+\r
+// U0BAUD (0xC2) - USART 0 Baud Rate Control\r
+\r
+// U1CSR (0xF8) - USART 1 Control and Status - bit accessible SFR register\r
+#define U1CSR_MODE                        0x80\r
+#define U1CSR_RE                          0x40\r
+#define U1CSR_SLAVE                       0x20\r
+#define U1CSR_FE                          0x10\r
+#define U1CSR_ERR                         0x08\r
+#define U1CSR_RX_BYTE                     0x04\r
+#define U1CSR_TX_BYTE                     0x02\r
+#define U1CSR_ACTIVE                      0x01\r
+\r
+\r
+// U1UCR (0xFB) - USART 1 UART Control\r
+#define U1UCR_FLUSH                       0x80\r
+#define U1UCR_FLOW                        0x40\r
+#define U1UCR_D9                          0x20\r
+#define U1UCR_BIT9                        0x10\r
+#define U1UCR_PARITY                      0x08\r
+#define U1UCR_SPB                         0x04\r
+#define U1UCR_STOP                        0x02\r
+#define U1UCR_START                       0x01\r
+\r
+\r
+// U1GCR (0xFC) - USART 1 Generic Control\r
+#define U1GCR_CPOL                        0x80\r
+#define U1GCR_CPHA                        0x40\r
+#define U1GCR_ORDER                       0x20\r
+#define U1GCR_BAUD_E                      0x1F\r
+#define U1GCR_BAUD_E0                     0x01\r
+#define U1GCR_BAUD_E1                     0x02\r
+#define U1GCR_BAUD_E2                     0x04\r
+#define U1GCR_BAUD_E3                     0x08\r
+#define U1GCR_BAUD_E4                     0x10\r
+\r
+\r
+// U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer\r
+\r
+// U1BAUD (0xFA) - USART 1 Baud Rate Control\r
+\r
+\r
+/*******************************************************************************\r
+ * I2S\r
+ */\r
+\r
+// 0xDF40: I2SCFG0 - I2S Configuration Register 0\r
+#define I2SCFG0_TXIEN                     0x80\r
+#define I2SCFG0_RXIEN                     0x40\r
+#define I2SCFG0_ULAWE                     0x20\r
+#define I2SCFG0_ULAWC                     0x10\r
+#define I2SCFG0_TXMONO                    0x08\r
+#define I2SCFG0_RXMONO                    0x04\r
+#define I2SCFG0_MASTER                    0x02\r
+#define I2SCFG0_ENAB                      0x01\r
+\r
+\r
+// 0xDF41: I2SCFG1 - I2S Configuration Register 1\r
+#define I2SCFG1_WORDS                     0xF8\r
+#define I2SCFG1_WORDS0                    0x08\r
+#define I2SCFG1_WORDS1                    0x10\r
+#define I2SCFG1_WORDS2                    0x20\r
+#define I2SCFG1_WORDS3                    0x40\r
+#define I2SCFG1_WORDS4                    0x80\r
+#define I2SCFG1_TRIGNUM                   0x06\r
+#define I2SCFG1_TRIGNUM0                  0x02\r
+#define I2SCFG1_TRIGNUM1                  0x04\r
+#define I2SCFG1_IOLOC                     0x01\r
+\r
+#define I2SCFG1_TRIGNUM_NO_TRIG           (0x00 << 1)\r
+#define I2SCFG1_TRIGNUM_USB_SOF           (0x01 << 1)\r
+#define I2SCFG1_TRIGNUM_IOC_1             (0x02 << 1)\r
+#define I2SCFG1_TRIGNUM_T1_CH0            (0x03 << 1)\r
+\r
+\r
+\r
+// 0xDF42: I2SDATL - I2S Data Low Byte\r
+\r
+// 0xDF43: I2SDATH - I2S Data High Byte\r
+\r
+// 0xDF44: I2SWCNT - I2S Word Count Register\r
+\r
+// 0xDF45: I2SSTAT - I2S Status Register\r
+#define I2SSTAT_TXUNF                     0x80\r
+#define I2SSTAT_RXOVF                     0x40\r
+#define I2SSTAT_TXLR                      0x20\r
+#define I2SSTAT_RXLR                      0x10\r
+#define I2SSTAT_TXIRQ                     0x08\r
+#define I2SSTAT_RXIRQ                     0x04\r
+#define I2SSTAT_WCNT                      0x03\r
+#define I2SSTAT_WCNT0                     0x01\r
+#define I2SSTAT_WCNT1                     0x02\r
+\r
+#define I2SSTAT_WCNT_10BIT                (0x02)\r
+#define I2SSTAT_WCNT_9BIT                 (0x01)\r
+#define I2SSTAT_WCNT_9_10BIT              (0x02)\r
+\r
+\r
+// 0xDF46: I2SCLKF0 - I2S Clock Configuration Register 0\r
+\r
+// 0xDF47: I2SCLKF1 - I2S Clock Configuration Register 1\r
+\r
+// 0xDF48: I2SCLKF2 - I2S Clock Configuration Register 2\r
+\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Radio Registers\r
+ */\r
+\r
+// RFIF (0xE9) - RF Interrupt Flags\r
+#define RFIF_IRQ_TXUNF                    0x80\r
+#define RFIF_IRQ_RXOVF                    0x40\r
+#define RFIF_IRQ_TIMEOUT                  0x20\r
+#define RFIF_IRQ_DONE                     0x10\r
+#define RFIF_IRQ_CS                       0x08\r
+#define RFIF_IRQ_PQT                      0x04\r
+#define RFIF_IRQ_CCA                      0x02\r
+#define RFIF_IRQ_SFD                      0x01\r
+\r
+\r
+// RFIM (0x91) - RF Interrupt Mask\r
+#define RFIM_IM_TXUNF                     0x80\r
+#define RFIM_IM_RXOVF                     0x40\r
+#define RFIM_IM_TIMEOUT                   0x20\r
+#define RFIM_IM_DONE                      0x10\r
+#define RFIM_IM_CS                        0x08\r
+#define RFIM_IM_PQT                       0x04\r
+#define RFIM_IM_CCA                       0x02\r
+#define RFIM_IM_SFD                       0x01\r
+\r
+\r
+// 0xDF2F: IOCFG2 - Radio Test Signal Configuration (P1_7)\r
+#define IOCFG2_GDO2_INV                   0x40\r
+#define IOCFG2_GDO2_CFG                   0x3F\r
+\r
+\r
+// 0xDF30: IOCFG1 - Radio Test Signal Configuration (P1_6)\r
+#define IOCFG1_GDO_DS                     0x80\r
+#define IOCFG1_GDO1_INV                   0x40\r
+#define IOCFG1_GDO1_CFG                   0x3F\r
+\r
+\r
+// 0xDF31: IOCFG0 - Radio Test Signal Configuration (P1_5)\r
+#define IOCFG0_GDO0_INV                   0x40\r
+#define IOCFG0_GDO0_CFG                   0x3F\r
+\r
+\r
+// 0xDF03: PKTCTRL1 - Packet Automation Control\r
+#define PKTCTRL1_PQT                      0xE0\r
+#define PKTCTRL1_PQT0                     0x20\r
+#define PKTCTRL1_PQT1                     0x40\r
+#define PKTCTRL1_PQT2                     0x80\r
+#define PKTCTRL1_APPEND_STATUS            0x04\r
+#define PKTCTRL1_ADR_CHK                  0x03\r
+#define PKTCTRL1_ADR_CHK0                 0x01\r
+#define PKTCTRL1_ADR_CHK1                 0x02\r
+\r
+#define ADR_CHK_NONE                      (0x00)\r
+#define ADR_CHK_NO_BRDCST                 (0x01)\r
+#define ADR_CHK_0_BRDCST                  (0x02)\r
+#define ADR_CHK_0_255_BRDCST              (0x03)\r
+\r
+\r
+// 0xDF04: PKTCTRL0 - Packet Automation Control\r
+#define PKTCTRL0_WHITE_DATA               0x40\r
+#define PKTCTRL0_PKT_FORMAT               0x30\r
+#define PKTCTRL0_PKT_FORMAT0              0x10\r
+#define PKTCTRL0_PKT_FORMAT1              0x20\r
+#define PKTCTRL0_CC2400_EN                0x08\r
+#define PKTCTRL0_CRC_EN                   0x04\r
+#define PKTCTRL0_LENGTH_CONFIG            0x03\r
+#define PKTCTRL0_LENGTH_CONFIG0           0x01\r
+\r
+#define PKT_FORMAT_NORM                   (0x00)\r
+#define PKT_FORMAT_RAND                   (0x02)\r
+\r
+#define PKTCTRL0_LENGTH_CONFIG_FIX        (0x00)\r
+#define PKTCTRL0_LENGTH_CONFIG_VAR        (0x01)\r
+\r
+\r
+// 0xDF05: ADDR - Device Address\r
+\r
+// 0xDF06: CHANNR - Channel Number\r
+\r
+// 0xDF07: FSCTRL1 - Frequency Synthesizer Control (only bit 0-4 used)\r
+\r
+// 0xDF08: FSCTRL0 - Frequency Synthesizer Control\r
+\r
+// 0xDF09: FREQ2 - Frequency Control Word, High Byte\r
+\r
+// 0xDF0A: FREQ1 - Frequency Control Word, Middle Byte\r
+\r
+// 0xDF0B: FREQ0 - Frequency Control Word, Low Byte\r
+\r
+// 0xDF0C: MDMCFG4 - Modem configuration\r
+\r
+// 0xDF0D: MDMCFG3 - Modem Configuration\r
+\r
+// 0xDF0E: MDMCFG2 - Modem Configuration\r
+#define MDMCFG2_DEM_DCFILT_OFF            0x80\r
+#define MDMCFG2_MOD_FORMAT                0x70\r
+#define MDMCFG2_MOD_FORMAT0               0x10\r
+#define MDMCFG2_MOD_FORMAT1               0x20\r
+#define MDMCFG2_MOD_FORMAT2               0x40\r
+#define MDMCFG2_MANCHESTER_EN             0x08\r
+#define MDMCFG2_SYNC_MODE                 0x07\r
+#define MDMCFG2_SYNC_MODE0                0x01\r
+#define MDMCFG2_SYNC_MODE1                0x02\r
+#define MDMCFG2_SYNC_MODE2                0x04\r
+\r
+#define MOD_FORMAT_2_FSK                  (0x00 << 4)\r
+#define MOD_FORMAT_GFSK                   (0x01 << 4)\r
+#define MOD_FORMAT_MSK                    (0x07 << 4)\r
+\r
+#define SYNC_MODE_NO_PRE                  (0x00)\r
+#define SYNC_MODE_15_16                   (0x01)\r
+#define SYNC_MODE_16_16                   (0x02)\r
+#define SYNC_MODE_30_32                   (0x03)\r
+#define SYNC_MODE_NO_PRE_CS               (0x04)    // CS = carrier-sense above threshold\r
+#define SYNC_MODE_15_16_CS                (0x05)\r
+#define SYNC_MODE_16_16_CS                (0x06)\r
+#define SYNC_MODE_30_32_CS                (0x07)\r
+\r
+\r
+// 0xDF0F: MDMCG1 - Modem Configuration\r
+#define MDMCG1_FEC_EN                     0x80\r
+#define MDMCG1_NUM_PREAMBLE               0x70\r
+#define MDMCG1_NUM_PREAMBLE0              0x10\r
+#define MDMCG1_NUM_PREAMBLE1              0x20\r
+#define MDMCG1_NUM_PREAMBLE2              0x40\r
+#define MDMCG1_CHANSPC_E                  0x03\r
+#define MDMCG1_CHANSPC_E0                 0x01\r
+#define MDMCG1_CHANSPC_E1                 0x02\r
+\r
+#define MDMCG1_NUM_PREAMBLE_2             (0x00 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_3             (0x01 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_4             (0x02 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_6             (0x03 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_8             (0x04 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_12            (0x05 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_16            (0x06 << 4)\r
+#define MDMCG1_NUM_PREAMBLE_24            (0x07 << 4)\r
+\r
+\r
+// 0xDF10: MDMCFG0 - Modem Configuration\r
+\r
+// 0xDF11: DEVIATN - Modem Deviation Setting\r
+#define DEVIATN_DEVIATION_E               0x70\r
+#define DEVIATN_DEVIATION_E0              0x10\r
+#define DEVIATN_DEVIATION_E1              0x20\r
+#define DEVIATN_DEVIATION_E2              0x40\r
+#define DEVIATN_DEVIATION_M               0x07\r
+#define DEVIATN_DEVIATION_M0              0x01\r
+#define DEVIATN_DEVIATION_M1              0x02\r
+#define DEVIATN_DEVIATION_M2              0x04\r
+\r
+\r
+// 0xDF12: MCSM2 - Main Radio Control State Machine Configuration\r
+#define MCSM2_RX_TIME_RSSI                0x10\r
+#define MCSM2_RX_TIME_QUAL                0x08\r
+#define MCSM2_RX_TIME                     0x07\r
+\r
+\r
+// 0xDF13: MCSM1 - Main Radio Control State Machine Configuration\r
+#define MCSM1_CCA_MODE                    0x30\r
+#define MCSM1_CCA_MODE0                   0x10\r
+#define MCSM1_CCA_MODE1                   0x20\r
+#define MCSM1_RXOFF_MODE                  0x0C\r
+#define MCSM1_RXOFF_MODE0                 0x04\r
+#define MCSM1_RXOFF_MODE1                 0x08\r
+#define MCSM1_TXOFF_MODE                  0x03\r
+#define MCSM1_TXOFF_MODE0                 0x01\r
+#define MCSM1_TXOFF_MODE1                 0x02\r
+\r
+#define MCSM1_CCA_MODE_ALWAYS             (0x00 << 4)\r
+#define MCSM1_CCA_MODE_RSSI0              (0x01 << 4)\r
+#define MCSM1_CCA_MODE_PACKET             (0x02 << 4)\r
+#define MCSM1_CCA_MODE_RSSI1              (0x03 << 4)\r
+\r
+#define MCSM1_RXOFF_MODE_IDLE             (0x00 << 2)\r
+#define MCSM1_RXOFF_MODE_FSTXON           (0x01 << 2)\r
+#define MCSM1_RXOFF_MODE_TX               (0x02 << 2)\r
+#define MCSM1_RXOFF_MODE_RX               (0x03 << 2)\r
+\r
+#define MCSM1_TXOFF_MODE_IDLE             (0x00 << 0)\r
+#define MCSM1_TXOFF_MODE_FSTXON           (0x01 << 0)\r
+#define MCSM1_TXOFF_MODE_TX               (0x02 << 0)\r
+#define MCSM1_TXOFF_MODE_RX               (0x03 << 0)\r
+\r
+\r
+// 0xDF14: MCSM0 - Main Radio Control State Machine Configuration\r
+#define MCSM0_FS_AUTOCAL                  0x30\r
+\r
+#define FS_AUTOCAL_NEVER                  (0x00 << 4)\r
+#define FS_AUTOCAL_FROM_IDLE              (0x01 << 4)\r
+#define FS_AUTOCAL_TO_IDLE                (0x02 << 4)\r
+#define FS_AUTOCAL_4TH_TO_IDLE            (0x03 << 4)\r
+\r
+\r
+// 0xDF15: FOCCFG - Frequency Offset Compensation Configuration\r
+#define FOCCFG_FOC_BS_CS_GATE             0x20\r
+#define FOCCFG_FOC_PRE_K                  0x18\r
+#define FOCCFG_FOC_PRE_K0                 0x08\r
+#define FOCCFG_FOC_PRE_K1                 0x10\r
+#define FOCCFG_FOC_POST_K                 0x04\r
+#define FOCCFG_FOC_LIMIT                  0x03\r
+#define FOCCFG_FOC_LIMIT0                 0x01\r
+#define FOCCFG_FOC_LIMIT1                 0x02\r
+\r
+#define FOC_PRE_K_1K                      (0x00 << 3)\r
+#define FOC_PRE_K_2K                      (0x02 << 3)\r
+#define FOC_PRE_K_3K                      (0x03 << 3)\r
+#define FOC_PRE_K_4K                      (0x04 << 3)\r
+\r
+#define FOC_LIMIT_0                       (0x00)\r
+#define FOC_LIMIT_DIV8                    (0x01)\r
+#define FOC_LIMIT_DIV4                    (0x02)\r
+#define FOC_LIMIT_DIV2                    (0x03)\r
+\r
+\r
+// 0xDF16: BSCFG - Bit Synchronization Configuration\r
+#define BSCFG_BS_PRE_KI                   0xC0\r
+#define BSCFG_BS_PRE_KI0                  0x40\r
+#define BSCFG_BS_PRE_KI1                  0x80\r
+#define BSCFG_BS_PRE_KP                   0x30\r
+#define BSCFG_BS_PRE_KP0                  0x10\r
+#define BSCFG_BS_PRE_KP1                  0x20\r
+#define BSCFG_BS_POST_KI                  0x08\r
+#define BSCFG_BS_POST_KP                  0x04\r
+#define BSCFG_BS_LIMIT                    0x03\r
+#define BSCFG_BS_LIMIT0                   0x01\r
+#define BSCFG_BS_LIMIT1                   0x02\r
+\r
+#define BSCFG_BS_PRE_KI_1K                (0x00 << 6)\r
+#define BSCFG_BS_PRE_KI_2K                (0x01 << 6)\r
+#define BSCFG_BS_PRE_KI_3K                (0x02 << 6)\r
+#define BSCFG_BS_PRE_KI_4K                (0x03 << 6)\r
+\r
+#define BSCFG_BS_PRE_KP_1K                (0x00 << 4)\r
+#define BSCFG_BS_PRE_KP_2K                (0x01 << 4)\r
+#define BSCFG_BS_PRE_KP_3K                (0x02 << 4)\r
+#define BSCFG_BS_PRE_KP_4K                (0x03 << 4)\r
+\r
+#define BSCFG_BS_LIMIT_0                  (0x00)\r
+#define BSCFG_BS_LIMIT_3                  (0x01)\r
+#define BSCFG_BS_LIMIT_6                  (0x02)\r
+#define BSCFG_BS_LIMIT_12                 (0x03)\r
+\r
+\r
+// 0xDF17: AGCCTRL2 - AGC Control\r
+#define AGCCTRL2_MAX_DVGA_GAIN            0xC0\r
+#define AGCCTRL2_MAX_LNA_GAIN             0x38\r
+#define AGCCTRL2_MAGN_TARGET              0x07\r
+\r
+\r
+// 0xDF18: AGCCTRL1 - AGC Control\r
+#define AGCCTRL1_AGC_LNA_PRIORITY         0x40\r
+#define AGCCTRL1_CARRIER_SENSE_REL_THR    0x30\r
+#define AGCCTRL1_CARRIER_SENSE_ABS_THR    0x0F\r
+\r
+\r
+// 0xDF19: AGCCTRL0 - AGC Control\r
+#define AGCCTRL0_HYST_LEVEL               0xC0\r
+#define AGCCTRL0_WAIT_TIME                0x30\r
+#define AGCCTRL0_AGC_FREEZE               0x0C\r
+#define AGCCTRL0_FILTER_LENGTH            0x03\r
+\r
+\r
+// 0xDF1A: FREND1 - Front End RX Configuration\r
+#define FREND1_LNA_CURRENT                0xC0\r
+#define FREND1_LNA2MIX_CURRENT            0x30\r
+#define FREND1_LODIV_BUF_CURRENT_RX       0x0C\r
+#define FREND1_MIX_CURRENT                0x03\r
+\r
+\r
+// 0xDF1B: FREND0 - Front End TX Configuration\r
+#define FREND0_LODIV_BUF_CURRENT_TX       0x30\r
+\r
+\r
+// 0xDF1C: FSCAL3 - Frequency Synthesizer Calibration\r
+#define FSCAL3_FSCAL3                     0xC0\r
+#define FSCAL3_CHP_CURR_CAL_EN            0x30\r
+\r
+\r
+// 0xDF1D: FSCAL2 - Frequency Synthesizer Calibration\r
+#define FSCAL2_VCO_CORE_H_EN              0x20\r
+#define FSCAL2_FSCAL2                     0x1F\r
+\r
+\r
+// 0xDF1E: FSCAL1 - Frequency Synthesizer Calibration\r
+\r
+// 0xDF1F: FSCAL0 - Frequency Synthesizer Calibration\r
+\r
+// 0xDF25: TEST0 - Various Test Settings\r
+\r
+\r
+// RFST (0xE1) - RF Strobe Commands\r
+#define RFST_SFSTXON                      0x00\r
+#define RFST_SCAL                         0x01\r
+#define RFST_SRX                          0x02\r
+#define RFST_STX                          0x03\r
+#define RFST_SIDLE                        0x04\r
+#define RFST_SNOP                         0x05\r
+\r
+// 0xDF3B: MARCSTATE - Main Radio Control State Machine State\r
+#define MARCSTATE_MARC_STATE              0x1F\r
+\r
+#define MARC_STATE_SLEEP                  0x00\r
+#define MARC_STATE_IDLE                   0x01\r
+#define MARC_STATE_VCOON_MC               0x03\r
+#define MARC_STATE_REGON_MC               0x04\r
+#define MARC_STATE_MANCAL                 0x05\r
+#define MARC_STATE_VCOON                  0x06\r
+#define MARC_STATE_REGON                  0x07\r
+#define MARC_STATE_STARTCAL               0x08\r
+#define MARC_STATE_BWBOOST                0x09\r
+#define MARC_STATE_FS_LOCK                0x0A\r
+#define MARC_STATE_IFADCON                0x0B\r
+#define MARC_STATE_ENDCAL                 0x0C\r
+#define MARC_STATE_RX                     0x0D\r
+#define MARC_STATE_RX_END                 0x0E\r
+#define MARC_STATE_RX_RST                 0x0F\r
+#define MARC_STATE_TXRX_SWITCH            0x10\r
+#define MARC_STATE_RX_OVERFLOW            0x11\r
+#define MARC_STATE_FSTXON                 0x12\r
+#define MARC_STATE_TX                     0x13\r
+#define MARC_STATE_TX_END                 0x14\r
+#define MARC_STATE_RXTX_SWITCH            0x15\r
+#define MARC_STATE_TX_UNDERFLOW           0x16\r
+\r
+\r
+\r
+/***********************************************************************/\r
+#endif\r

diff --git a/shellcode/chipcon/cc1110/specan.c b/shellcode/chipcon/cc1110/specan.c
new file mode 100644 (file)
index 0000000..fb778f7
--- /dev/null
+++ b/shellcode/chipcon/cc1110/specan.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2010 Michael Ossmann
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <cc1110.h>
+#include "ioCCxx10_bitdef.h"
+#include "specan.h"
+
+/* globals */
+__xdata channel_info chan_table[NUM_CHANNELS];
+u16 center_freq;
+u16 user_freq;
+u8 band;
+u8 width;
+__bit max_hold;
+__bit height;
+__bit sleepy;
+u8 vscroll;
+u8 min_chan;
+u8 max_chan;
+
+
+void sleepMillis(int ms) {
+  int j;
+  //k=1000;
+  //while(--k>0)
+  while (--ms > 0) { 
+    for (j=0; j<1200;j++); // about 1 millisecond
+  };
+}
+
+
+void radio_setup() {
+       /* IF of 457.031 kHz */
+       FSCTRL1 = 0x12;
+       FSCTRL0 = 0x00;
+
+       /* disable 3 highest DVGA settings */
+       AGCCTRL2 |= AGCCTRL2_MAX_DVGA_GAIN;
+
+       /* frequency synthesizer calibration */
+       FSCAL3 = 0xEA;
+       FSCAL2 = 0x2A;
+       FSCAL1 = 0x00;
+       FSCAL0 = 0x1F;
+
+       /* "various test settings" */
+       TEST2 = 0x88;
+       TEST1 = 0x31;
+       TEST0 = 0x09;
+
+       /* no automatic frequency calibration */
+       MCSM0 = 0;
+}
+
+/* set the channel bandwidth */
+void set_filter() {
+       /* channel spacing should fit within 80% of channel filter bandwidth */
+       switch (width) {
+       case NARROW:
+               MDMCFG4 = 0xEC; /* 67.708333 kHz */
+               break;
+       case ULTRAWIDE:
+               MDMCFG4 = 0x0C; /* 812.5 kHz */
+               break;
+       default:
+               MDMCFG4 = 0x6C; /* 270.833333 kHz */
+               break;
+       }
+}
+
+/* set the radio frequency in Hz */
+void set_radio_freq(u32 freq) {
+       /* the frequency setting is in units of 396.728515625 Hz */
+       u32 setting = (u32) (freq * .0025206154);
+       FREQ2 = (setting >> 16) & 0xff;
+       FREQ1 = (setting >> 8) & 0xff;
+       FREQ0 = setting & 0xff;
+
+       if ((band == BAND_300 && freq < MID_300) ||
+                       (band == BAND_400 && freq < MID_400) ||
+                       (band == BAND_900 && freq < MID_900))
+               /* select low VCO */
+               FSCAL2 = 0x0A;
+       else
+               /* select high VCO */
+               FSCAL2 = 0x2A;
+}
+
+/* freq in Hz */
+void calibrate_freq(u32 freq, u8 ch) {
+               set_radio_freq(freq);
+
+               RFST = RFST_SCAL;
+               RFST = RFST_SRX;
+
+               /* wait for calibration */
+               sleepMillis(2);
+
+               /* store frequency/calibration settings */
+               chan_table[ch].freq2 = FREQ2;
+               chan_table[ch].freq1 = FREQ1;
+               chan_table[ch].freq0 = FREQ0;
+               chan_table[ch].fscal3 = FSCAL3;
+               chan_table[ch].fscal2 = FSCAL2;
+               chan_table[ch].fscal1 = FSCAL1;
+
+               /* get initial RSSI measurement */
+               chan_table[ch].ss = (RSSI ^ 0x80);
+               chan_table[ch].max = 0;
+
+               RFST = RFST_SIDLE;
+}
+
+#define UPPER(a, b, c)  ((((a) - (b) + ((c) / 2)) / (c)) * (c))
+#define LOWER(a, b, c)  ((((a) + (b)) / (c)) * (c))
+
+/* set the center frequency in MHz */
+u16 set_center_freq(u16 freq) {
+       u8 new_band;
+       u32 spacing;
+       u32 hz;
+       u32 min_hz;
+       u32 max_hz;
+       u8 margin;
+       u8 step;
+       u16 upper_limit;
+       u16 lower_limit;
+       u16 next_up;
+       u16 next_down;
+       u8 next_band_up;
+       u8 next_band_down;
+
+       switch (width) {
+       case NARROW:
+               margin = NARROW_MARGIN;
+               step = NARROW_STEP;
+               spacing = NARROW_SPACING;
+               break;
+       case ULTRAWIDE:
+               margin = ULTRAWIDE_MARGIN;
+               step = ULTRAWIDE_STEP;
+               spacing = ULTRAWIDE_SPACING;
+
+               /* nearest 20 MHz step */
+               freq = ((freq + 10) / 20) * 20;
+               break;
+       default:
+               margin = WIDE_MARGIN;
+               step = WIDE_STEP;
+               spacing = WIDE_SPACING;
+
+               /* nearest 5 MHz step */
+               freq = ((freq + 2) / 5) * 5;
+               break;
+       }
+
+       /* handle cases near edges of bands */
+       if (freq > EDGE_900) {
+               new_band = BAND_900;
+               upper_limit = UPPER(MAX_900, margin, step);
+               lower_limit = LOWER(MIN_900, margin, step);
+               next_up = LOWER(MIN_300, margin, step);
+               next_down = UPPER(MAX_400, margin, step);
+               next_band_up = BAND_300;
+               next_band_down = BAND_400;
+       } else if (freq > EDGE_400) {
+               new_band = BAND_400;
+               upper_limit = UPPER(MAX_400, margin, step);
+               lower_limit = LOWER(MIN_400, margin, step);
+               next_up = LOWER(MIN_900, margin, step);
+               next_down = UPPER(MAX_300, margin, step);
+               next_band_up = BAND_900;
+               next_band_down = BAND_300;
+       } else {
+               new_band = BAND_300;
+               upper_limit = UPPER(MAX_300, margin, step);
+               lower_limit = LOWER(MIN_300, margin, step);
+               next_up = LOWER(MIN_400, margin, step);
+               next_down = UPPER(MAX_900, margin, step);
+               next_band_up = BAND_400;
+               next_band_down = BAND_900;
+       }
+
+       if (freq > upper_limit) {
+               freq = upper_limit;
+               if (new_band == band) {
+                       new_band = next_band_up;
+                       freq = next_up;
+               }
+       } else if (freq < lower_limit) {
+               freq = lower_limit;
+               if (new_band == band) {
+                       new_band = next_band_down;
+                       freq = next_down;
+               }
+       }
+
+       band = new_band;
+
+       /* doing everything in Hz from here on */
+       switch (band) {
+       case BAND_400:
+               min_hz = MIN_400 * 1000000;
+               max_hz = MAX_400 * 1000000;
+               break;
+       case BAND_300:
+               min_hz = MIN_300 * 1000000;
+               max_hz = MAX_300 * 1000000;
+               break;
+       default:
+               min_hz = MIN_900 * 1000000;
+               max_hz = MAX_900 * 1000000;
+               break;
+       }
+
+       /* calibrate upper channels */
+       hz = freq * 1000000;
+       max_chan = NUM_CHANNELS / 2;
+       while (hz <= max_hz && max_chan < NUM_CHANNELS) {
+               calibrate_freq(hz, max_chan);
+               hz += spacing;
+               max_chan++;
+       }
+
+       /* calibrate lower channels */
+       hz = freq * 1000000 - spacing;
+       min_chan = NUM_CHANNELS / 2;
+       while (hz >= min_hz && min_chan > 0) {
+               min_chan--;
+               calibrate_freq(hz, min_chan);
+               hz -= spacing;
+       }
+
+       center_freq = freq;
+       max_hold = 0;
+
+       return freq;
+}
+
+/* tune the radio using stored calibration */
+void tune(u8 ch) {
+       FREQ2 = chan_table[ch].freq2;
+       FREQ1 = chan_table[ch].freq1;
+       FREQ0 = chan_table[ch].freq0;
+
+       FSCAL3 = chan_table[ch].fscal3;
+       FSCAL2 = chan_table[ch].fscal2;
+       FSCAL1 = chan_table[ch].fscal1;
+}
+
+void set_width(u8 w) {
+       width = w;
+       set_filter();
+       set_center_freq(center_freq);
+}
+
+void poll_keyboard() {
+  /*
+       u8 vstep;
+       u8 hstep;
+
+       vstep = (height == TALL) ? TALL_STEP : SHORT_STEP;
+
+       switch (width) {
+       case NARROW:
+               hstep = NARROW_STEP;
+               break;
+       case ULTRAWIDE:
+               hstep = ULTRAWIDE_STEP;
+               break;
+       default:
+               hstep = WIDE_STEP;
+               break;
+       }
+
+       switch (getkey()) {
+       case 'W':
+               set_width(WIDE);
+               break;
+       case 'N':
+               set_width(NARROW);
+               break;
+       case 'U':
+               set_width(ULTRAWIDE);
+               break;
+        case KMNU:
+               switch (width) {
+               case WIDE:
+                       set_width(NARROW);
+                       break;
+               case NARROW:
+                       set_width(ULTRAWIDE);
+                       break;
+               default:
+                       set_width(WIDE);
+                       break;
+               }
+               break;
+       case 'T':
+               height = TALL;
+               break;
+       case 'S':
+               height = SHORT;
+               break;
+       case KBYE:
+               height = !height;
+               break;
+       case '>':
+               user_freq += hstep;
+               break;
+       case '<':
+               user_freq -= hstep;
+               break;
+       case '^':
+       case 'Q':
+               vscroll = MIN(vscroll + vstep, MAX_VSCROLL);
+               break;
+       case KDWN:
+       case 'A':
+               vscroll = MAX(vscroll - vstep, MIN_VSCROLL);
+               break;
+       case 'M':
+               max_hold = !max_hold;
+               break;
+       case KPWR:
+               sleepy = 1;
+               break;
+       default:
+               break;
+       }
+  */
+}
+
+void main(void) {
+       u8 ch;
+       u16 i;
+
+reset:
+       center_freq = DEFAULT_FREQ;
+       user_freq = DEFAULT_FREQ;
+       band = BAND_900;
+       width = WIDE;
+       max_hold = 0;
+       height = 0;
+       sleepy = 0;
+       vscroll = 0;
+       min_chan = 0;
+       max_chan = NUM_CHANNELS - 1;
+       
+       //presumed to be done by GoodFET.
+       //xtalClock(); 
+       //setIOPorts();
+       radio_setup();
+       set_width(WIDE);
+
+       while (1) {
+               for (ch = min_chan; ch < max_chan; ch++) {
+                       /* tune radio and start RX */
+                       tune(ch);
+                       RFST = RFST_SRX;
+
+                       /* delay while waiting for RSSI measurement */
+                       sleepMillis(10);
+                       
+                       /* measurement needs a bit more time in narrow mode */
+                       if (width == NARROW)
+                               for (i = 350; i-- ;);
+
+                       /* read RSSI */
+                       chan_table[ch].ss = (RSSI ^ 0x80);
+                       if (max_hold)
+                               chan_table[ch].max = MAX(chan_table[ch].ss,
+                                               chan_table[ch].max);
+                       else
+                               chan_table[ch].max = 0;
+
+                       /* end RX */
+                       RFST = RFST_SIDLE;
+               }
+
+               poll_keyboard();
+
+
+               if (user_freq != center_freq)
+                       user_freq = set_center_freq(user_freq);
+       }
+}

diff --git a/shellcode/chipcon/cc1110/specan.h b/shellcode/chipcon/cc1110/specan.h
new file mode 100644 (file)
index 0000000..5910901
--- /dev/null
+++ b/shellcode/chipcon/cc1110/specan.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2010 Michael Ossmann
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#define u8 unsigned char
+#define u16 unsigned int
+#define u32 unsigned long
+
+/*
+ * There is one channel per column of the display.  The radio is tuned to one
+ * channel at a time and RSSI is displayed for that channel.
+ */
+#define NUM_CHANNELS 132
+
+/*
+ * wide mode (default): 44 MHz on screen, 333 kHz per channel
+ * narrow mode: 6.6 MHz on screen, 50 kHz per channel
+ */
+#define WIDE 0
+#define NARROW 1
+#define ULTRAWIDE 2
+
+/*
+ * short mode (default): displays RSSI >> 2
+ * tall mode: displays RSSI
+ */
+#define SHORT 0
+#define TALL 1
+
+/* vertical scrolling */
+#define SHORT_STEP  16
+#define TALL_STEP   4
+#define MAX_VSCROLL 208
+#define MIN_VSCROLL 0
+
+/* frequencies in MHz */
+#define DEFAULT_FREQ     915
+#define WIDE_STEP        5
+#define NARROW_STEP      1
+#define ULTRAWIDE_STEP   20
+#define WIDE_MARGIN      13
+#define NARROW_MARGIN    3
+#define ULTRAWIDE_MARGIN 42
+
+/* frequency bands supported by device */
+#define BAND_300 0
+#define BAND_400 1
+#define BAND_900 2
+
+/* band limits in MHz */
+#define MIN_300  281
+#define MAX_300  361
+#define MIN_400  378
+#define MAX_400  481
+#define MIN_900  749
+#define MAX_900  962
+
+/* band transition points in MHz */
+#define EDGE_400 369
+#define EDGE_900 615
+
+/* VCO transition points in Hz */
+#define MID_300  318000000
+#define MID_400  424000000
+#define MID_900  848000000
+
+/* channel spacing in Hz */
+#define WIDE_SPACING      199952
+#define NARROW_SPACING    49988
+#define ULTRAWIDE_SPACING 666504
+
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+
+
+/* Keeping track of all this for each channel allows us to tune faster. */
+typedef struct {
+       /* frequency setting */
+       u8 freq2;
+       u8 freq1;
+       u8 freq0;
+       
+       /* frequency calibration */
+       u8 fscal3;
+       u8 fscal2;
+       u8 fscal1;
+
+       /* signal strength */
+       u8 ss;
+       u8 max;
+} channel_info;
+
+void clear();
+void plot(u8 col);
+void putchar(char c);
+u8 getkey();
+void draw_ruler();
+void draw_freq();
+void radio_setup();
+void set_filter();
+void set_radio_freq(u32 freq);
+void calibrate_freq(u32 freq, u8 ch);
+u16 set_center_freq(u16 freq);
+void tune(u8 ch);
+void set_width(u8 w);
+void poll_keyboard();
+void main(void);