From: Michel Pollet Date: Thu, 3 Dec 2009 23:56:57 +0000 (+0000) Subject: tiny25/45 cores added X-Git-Url: http://git.rot13.org/?a=commitdiff_plain;h=4acd890a940f5f0cc5a028017aa6b6d3136c33c8;p=simavr tiny25/45 cores added Same method as the mega48/88/168... Signed-off-by: Jon Escombe Signed-off-by: Michel Pollet --- diff --git a/simavr/cores/sim_tiny25.c b/simavr/cores/sim_tiny25.c new file mode 100644 index 0000000..5c32576 --- /dev/null +++ b/simavr/cores/sim_tiny25.c @@ -0,0 +1,44 @@ +/* + sim_tiny25.c + + Copyright 2008, 2009 Michel Pollet + Jon Escombe + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "sim_avr.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "attiny25" +#define SIM_CORENAME mcu_tiny25 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iotn25.h" +// instanciate the new core +#include "sim_tinyx5.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t tiny25 = { + .names = { "attiny25" }, + .make = make +}; + diff --git a/simavr/cores/sim_tiny45.c b/simavr/cores/sim_tiny45.c new file mode 100644 index 0000000..1500b54 --- /dev/null +++ b/simavr/cores/sim_tiny45.c @@ -0,0 +1,44 @@ +/* + sim_tiny45.c + + Copyright 2008, 2009 Michel Pollet + Jon Escombe + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "sim_avr.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "attiny45" +#define SIM_CORENAME mcu_tiny45 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iotn45.h" +// instanciate the new core +#include "sim_tinyx5.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t tiny45 = { + .names = { "attiny45" }, + .make = make +}; + diff --git a/simavr/cores/sim_tiny85.c b/simavr/cores/sim_tiny85.c index aac8299..1508a4f 100644 --- a/simavr/cores/sim_tiny85.c +++ b/simavr/cores/sim_tiny85.c @@ -2,6 +2,7 @@ sim_tiny85.c Copyright 2008, 2009 Michel Pollet + Jon Escombe This file is part of simavr. @@ -19,104 +20,21 @@ along with simavr. If not, see . */ -#include #include "sim_avr.h" -#include "sim_core_declare.h" -#include "avr_eeprom.h" -#include "avr_ioport.h" -#include "avr_timer8.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "attiny85" +#define SIM_CORENAME mcu_tiny85 #define _AVR_IO_H_ #define __ASSEMBLER__ #include "avr/iotn85.h" - -static void init(struct avr_t * avr); -static void reset(struct avr_t * avr); - - -static struct mcu_t { - avr_t core; - avr_eeprom_t eeprom; - avr_ioport_t portb; - avr_timer8_t timer0, timer1; -} mcu = { - .core = { - .mmcu = "attiny85", - DEFAULT_CORE(2), - - .init = init, - .reset = reset, - }, - AVR_EEPROM_DECLARE(EE_RDY_vect), - .portb = { - .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, - .pcint = { - .enable = AVR_IO_REGBIT(GIMSK, PCIE), - .raised = AVR_IO_REGBIT(GIFR, PCIF), - .vector = PCINT0_vect, - }, - .r_pcint = PCMSK, - }, - .timer0 = { - .name = '0', - .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, - .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) }, - .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, - - .r_ocra = OCR0A, - .r_ocrb = OCR0B, - .r_tcnt = TCNT0, - - .overflow = { - .enable = AVR_IO_REGBIT(TIMSK, TOIE0), - .raised = AVR_IO_REGBIT(TIFR, TOV0), - .vector = TIMER0_OVF_vect, - }, - .compa = { - .enable = AVR_IO_REGBIT(TIMSK, OCIE0A), - .raised = AVR_IO_REGBIT(TIFR, OCF0A), - .vector = TIMER0_COMPA_vect, - }, - .compb = { - .enable = AVR_IO_REGBIT(TIMSK, OCIE0B), - .raised = AVR_IO_REGBIT(TIFR, OCF0B), - .vector = TIMER0_COMPB_vect, - }, - }, - .timer1 = { - .name = '1', - // no wgm bits - .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) }, - .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ }, - - .r_ocra = OCR1A, - .r_ocrb = OCR1B, - .r_ocrc = OCR1C, - .r_tcnt = TCNT1, - - .overflow = { - .enable = AVR_IO_REGBIT(TIMSK, TOIE1), - .raised = AVR_IO_REGBIT(TIFR, TOV1), - .vector = TIMER1_OVF_vect, - }, - .compa = { - .enable = AVR_IO_REGBIT(TIMSK, OCIE1A), - .raised = AVR_IO_REGBIT(TIFR, OCF1A), - .vector = TIMER1_COMPA_vect, - }, - .compb = { - .enable = AVR_IO_REGBIT(TIMSK, OCIE1B), - .raised = AVR_IO_REGBIT(TIFR, OCF1B), - .vector = TIMER1_COMPB_vect, - }, - }, - - -}; +// instanciate the new core +#include "sim_tinyx5.h" static avr_t * make() { - return &mcu.core; + return &SIM_CORENAME.core; } avr_kind_t tiny85 = { @@ -124,19 +42,3 @@ avr_kind_t tiny85 = { .make = make }; -static void init(struct avr_t * avr) -{ - struct mcu_t * mcu = (struct mcu_t*)avr; - - printf("%s init\n", avr->mmcu); - - avr_eeprom_init(avr, &mcu->eeprom); - avr_ioport_init(avr, &mcu->portb); - avr_timer8_init(avr, &mcu->timer0); - avr_timer8_init(avr, &mcu->timer1); -} - -static void reset(struct avr_t * avr) -{ -// struct mcu_t * mcu = (struct mcu_t*)avr; -} diff --git a/simavr/cores/sim_tinyx5.c b/simavr/cores/sim_tinyx5.c new file mode 100644 index 0000000..7b5e039 --- /dev/null +++ b/simavr/cores/sim_tinyx5.c @@ -0,0 +1,43 @@ +/* + sim_tinyx5.c + + Copyright 2008, 2009 Michel Pollet + Jon Escombe + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "sim_avr.h" + +#include "sim_tinyx5.h" + +void tx5_init(struct avr_t * avr) +{ + struct mcu_t * mcu = (struct mcu_t*)avr; + + printf("%s init\n", avr->mmcu); + + avr_eeprom_init(avr, &mcu->eeprom); + avr_ioport_init(avr, &mcu->portb); + avr_timer8_init(avr, &mcu->timer0); + avr_timer8_init(avr, &mcu->timer1); +} + +void tx5_reset(struct avr_t * avr) +{ +// struct mcu_t * mcu = (struct mcu_t*)avr; +} diff --git a/simavr/cores/sim_tinyx5.h b/simavr/cores/sim_tinyx5.h new file mode 100644 index 0000000..aeb9d8a --- /dev/null +++ b/simavr/cores/sim_tinyx5.h @@ -0,0 +1,130 @@ +/* + sim_tinyx5.h + + Copyright 2008, 2009 Michel Pollet + Jon Escombe + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + + +#ifndef __SIM_TINYX5_H__ +#define __SIM_TINYX5_H__ + +#include "sim_core_declare.h" +#include "avr_eeprom.h" +#include "avr_ioport.h" +#include "avr_timer8.h" + +void tx5_init(struct avr_t * avr); +void tx5_reset(struct avr_t * avr); + +/* + * This is a template for all of the tinyx5 devices, hopefully + */ +struct mcu_t { + avr_t core; + avr_eeprom_t eeprom; + avr_ioport_t portb; + avr_timer8_t timer0, timer1; +}; + +#ifdef SIM_CORENAME + +#ifndef SIM_VECTOR_SIZE +#error SIM_VECTOR_SIZE is not declared +#endif +#ifndef SIM_MMCU +#error SIM_MMCU is not declared +#endif + +struct mcu_t SIM_CORENAME = { + .core = { + .mmcu = SIM_MMCU, + DEFAULT_CORE(SIM_VECTOR_SIZE), + + .init = tx5_init, + .reset = tx5_reset, + }, + AVR_EEPROM_DECLARE(EE_RDY_vect), + .portb = { + .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, + .pcint = { + .enable = AVR_IO_REGBIT(GIMSK, PCIE), + .raised = AVR_IO_REGBIT(GIFR, PCIF), + .vector = PCINT0_vect, + }, + .r_pcint = PCMSK, + }, + .timer0 = { + .name = '0', + .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, + .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR0A, + .r_ocrb = OCR0B, + .r_tcnt = TCNT0, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE0), + .raised = AVR_IO_REGBIT(TIFR, TOV0), + .vector = TIMER0_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE0A), + .raised = AVR_IO_REGBIT(TIFR, OCF0A), + .vector = TIMER0_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE0B), + .raised = AVR_IO_REGBIT(TIFR, OCF0B), + .vector = TIMER0_COMPB_vect, + }, + }, + .timer1 = { + .name = '1', + // no wgm bits + .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) }, + .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ }, + + .r_ocra = OCR1A, + .r_ocrb = OCR1B, + .r_ocrc = OCR1C, + .r_tcnt = TCNT1, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE1), + .raised = AVR_IO_REGBIT(TIFR, TOV1), + .vector = TIMER1_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1A), + .raised = AVR_IO_REGBIT(TIFR, OCF1A), + .vector = TIMER1_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1B), + .raised = AVR_IO_REGBIT(TIFR, OCF1B), + .vector = TIMER1_COMPB_vect, + }, + }, + + +}; +#endif /* SIM_CORENAME */ + +#endif /* __SIM_TINYX5_H__ */ diff --git a/simavr/sim/sim_avr.c b/simavr/sim/sim_avr.c index 46ed8de..a4fa2b2 100644 --- a/simavr/sim/sim_avr.c +++ b/simavr/sim/sim_avr.c @@ -188,11 +188,13 @@ int avr_run(avr_t * avr) } -extern avr_kind_t tiny85; +extern avr_kind_t tiny25,tiny45,tiny85; extern avr_kind_t mega48,mega88,mega168; extern avr_kind_t mega644; avr_kind_t * avr_kind[] = { + &tiny25, + &tiny45, &tiny85, &mega48, &mega88,