From: Michel Pollet Date: Tue, 24 Nov 2009 13:11:54 +0000 (+0000) Subject: Initial Commit X-Git-Url: http://git.rot13.org/?a=commitdiff_plain;h=d8e5774323d5408e119b5fa3cce1c73c7345e8f7;p=simavr Initial Commit Signed-off-by: Michel Pollet --- d8e5774323d5408e119b5fa3cce1c73c7345e8f7 diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..0bfb771 --- /dev/null +++ b/.cproject @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b3de6c0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +obj +*.axf +*.hex +*.s +simavr/simavr diff --git a/.project b/.project new file mode 100644 index 0000000..59cd1bd --- /dev/null +++ b/.project @@ -0,0 +1,77 @@ + + + simavr + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + jap make -C Sources/Utils/simavr + + + org.eclipse.cdt.make.core.buildCommand + ssh + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.simavr.jcc b/.simavr.jcc new file mode 100644 index 0000000..640d586 --- /dev/null +++ b/.simavr.jcc @@ -0,0 +1,140 @@ +jx_browser_data 79 +# project tree +0 "root" +T +1 "main" +T +2 "Makefile" +F +"./simavr/Makefile" +T +2 "avr_spi.c" +F +"./simavr/sim/avr_spi.c" +T +2 "avr_spi.h" +F +"./simavr/sim/avr_spi.h" +T +2 "avr_timer8.c" +F +"./simavr/sim/avr_timer8.c" +T +2 "avr_timer8.h" +F +"./simavr/sim/avr_timer8.h" +T +2 "avr_ioport.c" +F +"./simavr/sim/avr_ioport.c" +T +2 "avr_ioport.h" +F +"./simavr/sim/avr_ioport.h" +T +2 "avr_eeprom.c" +F +"./simavr/sim/avr_eeprom.c" +T +2 "avr_eeprom.h" +F +"./simavr/sim/avr_eeprom.h" +T +2 "avr_uart.c" +F +"./simavr/sim/avr_uart.c" +T +2 "avr_uart.h" +F +"./simavr/sim/avr_uart.h" +T +2 "sim_core.c" +F +"./simavr/sim/sim_core.c" +T +2 "sim_core.h" +F +"./simavr/sim/sim_core.h" +T +2 "sim_gdb.c" +F +"./simavr/sim/sim_gdb.c" +T +2 "sim_gdb.h" +F +"./simavr/sim/sim_gdb.h" +T +2 "sim_elf.c" +F +"./simavr/sim/sim_elf.c" +T +2 "sim_elf.h" +F +"./simavr/sim/sim_elf.h" +T +2 "simavr.c" +F +"./simavr/sim/simavr.c" +T +2 "simavr.h" +F +"./simavr/sim/simavr.h" +F +T +1 "tests" +T +2 "atmega88_example.c" +F +"./tests/atmega88_example.c" +F +T +1 "cores" +T +2 "sim_core_declare.h" +F +"./simavr/cores/sim_core_declare.h" +T +2 "sim_mega88.c" +F +"./simavr/cores/sim_mega88.c" +T +2 "sim_mega168.c" +F +"./simavr/cores/sim_mega168.c" +T +2 "sim_mega48.c" +F +"./simavr/cores/sim_mega48.c" +T +2 "sim_megax8.c" +F +"./simavr/cores/sim_megax8.c" +T +2 "sim_megax8.h" +F +"./simavr/cores/sim_megax8.h" +T +2 "sim_tiny85.c" +F +"./simavr/cores/sim_tiny85.c" +T +2 "sim_mega644.c" +F +"./simavr/cores/sim_mega644.c" +F +F +# tasks +4 +"echo Makefile must be updated manually" +F +# build settings +0 +T +"simavr" +"" +"make -k all" +# search paths +T "./" T +F +# C preprocessor +F diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..94a9ed0 --- /dev/null +++ b/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..cd3b15b --- /dev/null +++ b/Makefile @@ -0,0 +1,12 @@ + + +all: make-tests + make -C simavr + +make-tests: + make -C tests + +clean: + make -C simavr clean + make -C tests clean + \ No newline at end of file diff --git a/README b/README new file mode 100644 index 0000000..7aaa72f --- /dev/null +++ b/README @@ -0,0 +1,35 @@ + +simavr -- a simple, lean and mean AVR simulator + +http://gitorious.org/simavr + +simavr is a new AVR simulator for linux, or any platform that uses avr-gcc. It uses +avr-gcc own register definition to simplify creating new targets for supoortted AVR +devices. + +The core was made to be small and compact, and hackable so allow quick protoyping +of an AVR project. The simulator loads .elf directly, and there is even a way to +specify simulation parameters directly in the emulated code using an .elf section. + +The status of the project is the core works at about 98% (ie, it works, but there +is a known bug). The supported IOs are eeprom, IO ports (including pin interupts), +8 bits timers (well, one of mode of the myriad) and a simple UART that makes +ÒprintfÓ work. + +gdb support is planned next. + +PREQUISTES: ++ avr-gcc ; tested with 4.3.4 (from debian) + The code rudely assumes the avr-gcc is in /usr/lib/avr/include/... ++ libelf-dev + +BUILD: ++ make + +TEST: ++ ./simavr/simavr tests/atmega88_example.axf + +There are no command line options for now.. The simulator recognizes attiny85, +atmega48,88,168 and atmega644. It's fairly easy to add new cores. + +Michel Pollet diff --git a/include/avr_mcu_section.h b/include/avr_mcu_section.h new file mode 100644 index 0000000..b20d501 --- /dev/null +++ b/include/avr_mcu_section.h @@ -0,0 +1,55 @@ +/* + avr_mcu_section.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __AVR_MCU_SECTION_H__ +#define __AVR_MCU_SECTION_H__ + +/* + * This structure is used to pass "parameters" to the programmer or the simulator, + * it tags the ELF file with a section that contains parameters about the physical + * AVR this was compiled for, including the speed, model, and signature bytes. + * + * A programmer software can read this and verify fuses values for example, and a + * simulator can instanciate the proper "model" of AVR, the speed and so on without + * command line parameters. + * + * Exemple of use: + * + * #include "avr_mcu_section.h" + * AVR_MCU(F_CPU, "atmega88"); + * + */ + +typedef struct avr_mcu_t { + long f_cpu; // avr is little endian + unsigned char id[4]; // signature bytes + unsigned char fuse[4]; // optional + char name[16]; +} avr_mcu_t; + +#define AVR_MCU(_speed, _name) \ +const avr_mcu_t _mmcu __attribute__((section(".mmcu"))) = {\ + .f_cpu = _speed, \ + .id = {SIGNATURE_0, SIGNATURE_1, SIGNATURE_2}, \ + .name = _name,\ +} + +#endif diff --git a/simavr/Makefile b/simavr/Makefile new file mode 100644 index 0000000..b076154 --- /dev/null +++ b/simavr/Makefile @@ -0,0 +1,70 @@ +# +# Copyright 2008, 2009 Michel Pollet +# +# This file is part of simavr. +# +# simavr is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# simavr is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with simavr. If not, see . + +target = simavr + +CFLAGS = -g -std=gnu99 -Wall +CFLAGS += -O3 -mfpmath=sse -msse2 + +cores = ${wildcard cores/*.c} +cores_o = ${patsubst cores/%.c, obj/%.o, ${cores}} +sim = ${wildcard sim/*.c} +sim_o = ${patsubst sim/%.c, obj/%.o, ${sim}} + +VPATH = . +VPATH += cores +VPATH += sim + +IPATH = . +IPATH += sim +IPATH += ../../shared +IPATH += ../include +IPATH += /opt/local/include + +CFLAGS += ${patsubst %,-I%,${subst :, ,${IPATH}}} +LFLAGS = -L/opt/local/lib/ +LDFLAGS += -lelf + +all: obj ${target} + +obj: + @mkdir -p obj + +obj/sim_%.o : cores/sim_%.h cores/sim_core_declare.h sim/*.h +obj/sim_%.o : cores/sim_%.c + @gcc $(CFLAGS) \ + -I/usr/lib/avr/include/ \ + $< -c -o $@ + @echo CORE $< + +obj/%.o: %.h sim/*.h +obj/%.o: %.c + @gcc $(CFLAGS) \ + $< -c -o $@ + @echo CC $< + +${target} : ${cores_o} +${target} : ${sim_o} + @gcc $(CFLAGS) $(LFLAGS) \ + ${^} -o $@ \ + $(LDFLAGS) + @echo LD $@ + +clean: + rm -rf ${target} obj + diff --git a/simavr/cores/sim_core_declare.h b/simavr/cores/sim_core_declare.h new file mode 100644 index 0000000..4394c89 --- /dev/null +++ b/simavr/cores/sim_core_declare.h @@ -0,0 +1,45 @@ +/* + sim_core_declare.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ +#ifndef __SIM_CORE_DECLARE_H__ +#define __SIM_CORE_DECLARE_H__ + +/* + * The macros "fake" the ones in the real avrlib + */ +#define _SFR_IO8(v) ((v)+32) +#define _SFR_MEM8(v) (v) +#define _BV(v) (v) +#define _VECTOR(v) (v) + +/* + * This declares a typical AVR core, using constants what appears + * to be in every io*.h file... + */ +#define DEFAULT_CORE(_vector_size) \ + .ramend = RAMEND, \ + .flashend = FLASHEND, \ + .e2end = E2END, \ + .vector_size = _vector_size, \ + .signature = { SIGNATURE_0,SIGNATURE_1,SIGNATURE_2 }, \ + .fuse = { LFUSE_DEFAULT, HFUSE_DEFAULT, EFUSE_DEFAULT } + + +#endif /* __SIM_CORE_DECLARE_H__ */ diff --git a/simavr/cores/sim_mega168.c b/simavr/cores/sim_mega168.c new file mode 100644 index 0000000..54d8bcf --- /dev/null +++ b/simavr/cores/sim_mega168.c @@ -0,0 +1,43 @@ +/* + sim_mega168.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "simavr.h" + +#define SIM_VECTOR_SIZE 4 +#define SIM_MMCU "atmega168" +#define SIM_CORENAME mcu_mega168 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom168.h" +// instanciate the new core +#include "sim_megax8.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t mega168 = { + .names = { "atmega168", "atmega168p","atmega168pa" }, + .make = make +}; + diff --git a/simavr/cores/sim_mega48.c b/simavr/cores/sim_mega48.c new file mode 100644 index 0000000..b0b0c95 --- /dev/null +++ b/simavr/cores/sim_mega48.c @@ -0,0 +1,43 @@ +/* + sim_mega48.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "simavr.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "atmega48" +#define SIM_CORENAME mcu_mega48 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom48.h" +// instanciate the new core +#include "sim_megax8.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t mega48 = { + .names = { "atmega48", "atmega48p","atmega48pa" }, + .make = make +}; + diff --git a/simavr/cores/sim_mega644.c b/simavr/cores/sim_mega644.c new file mode 100644 index 0000000..813e551 --- /dev/null +++ b/simavr/cores/sim_mega644.c @@ -0,0 +1,240 @@ +/* + sim_mega644.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "simavr.h" +#include "sim_core_declare.h" +#include "avr_eeprom.h" +#include "avr_ioport.h" +#include "avr_uart.h" +#include "avr_timer8.h" + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom644.h" + +static void init(struct avr_t * avr); +static void reset(struct avr_t * avr); + + +static struct mcu_t { + avr_t core; + avr_eeprom_t eeprom; + avr_ioport_t porta, portb, portc, portd; + avr_uart_t uart0,uart1; + avr_timer8_t timer0,timer2; +} mcu = { + .core = { + .mmcu = "atmega644", + DEFAULT_CORE(4), + + .init = init, + .reset = reset, + }, + .eeprom = { + .size = E2END+1, + .r_eearh = EEARH, + .r_eearl = EEARL, + .r_eedr = EEDR, + .r_eecr = EECR, + .eepm = { AVR_IO_REGBIT(EECR, EEPM0), AVR_IO_REGBIT(EECR, EEPM1) }, + .eempe = AVR_IO_REGBIT(EECR, EEMPE), + .eepe = AVR_IO_REGBIT(EECR, EEPE), + .eere = AVR_IO_REGBIT(EECR, EERE), + .ready = { + .enable = AVR_IO_REGBIT(EECR, EERIE), + .vector = EE_READY_vect, + }, + }, + .porta = { + .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE0), + .raised = AVR_IO_REGBIT(PCIFR, PCIF0), + .vector = PCINT0_vect, + }, + .r_pcint = PCMSK0, + }, + .portb = { + .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE1), + .raised = AVR_IO_REGBIT(PCIFR, PCIF1), + .vector = PCINT1_vect, + }, + .r_pcint = PCMSK1, + }, + .portc = { + .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE2), + .raised = AVR_IO_REGBIT(PCIFR, PCIF2), + .vector = PCINT2_vect, + }, + .r_pcint = PCMSK2, + }, + .portd = { + .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE3), + .raised = AVR_IO_REGBIT(PCIFR, PCIF3), + .vector = PCINT3_vect, + }, + .r_pcint = PCMSK3, + }, + + .uart0 = { + .disabled = AVR_IO_REGBIT(PRR,PRUSART0), + .name = '0', + .r_udr = UDR0, + .udre = AVR_IO_REGBIT(UCSR0A, UDRE0), + + .r_ucsra = UCSR0A, + .r_ucsrb = UCSR0B, + .r_ucsrc = UCSR0C, + .r_ubrrl = UBRR0L, + .r_ubrrh = UBRR0H, + .rxc = { + .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0), + .vector = USART0_RX_vect, + }, + .txc = { + .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0), + .vector = USART0_TX_vect, + }, + .udrc = { + .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0), + .vector = USART0_UDRE_vect, + }, + }, + .uart1 = { + .disabled = AVR_IO_REGBIT(PRR,PRUSART1), + .name = '1', + .r_udr = UDR1, + .udre = AVR_IO_REGBIT(UCSR1A, UDRE1), + + .r_ucsra = UCSR1A, + .r_ucsrb = UCSR1B, + .r_ucsrc = UCSR1C, + .r_ubrrl = UBRR1L, + .r_ubrrh = UBRR1H, + .rxc = { + .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1), + .vector = USART1_RX_vect, + }, + .txc = { + .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1), + .vector = USART1_TX_vect, + }, + .udrc = { + .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1), + .vector = USART1_UDRE_vect, + }, + }, + + .timer0 = { + .name = '0', + .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, + .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR0A, + .r_ocrb = OCR0B, + .r_tcnt = TCNT0, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK0, TOIE0), + .raised = AVR_IO_REGBIT(TIFR0, TOV0), + .vector = TIMER0_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A), + .raised = AVR_IO_REGBIT(TIFR0, OCF0A), + .vector = TIMER0_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B), + .raised = AVR_IO_REGBIT(TIFR0, OCF0B), + .vector = TIMER0_COMPB_vect, + }, + }, + .timer2 = { + .name = '2', + .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) }, + .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) }, + .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR2A, + .r_ocrb = OCR2B, + .r_tcnt = TCNT2, + + // asynchronous timer source bit.. if set, use 32khz frequency + .as2 = AVR_IO_REGBIT(ASSR, AS2), + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK2, TOIE2), + .raised = AVR_IO_REGBIT(TIFR2, TOV2), + .vector = TIMER2_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A), + .raised = AVR_IO_REGBIT(TIFR2, OCF2A), + .vector = TIMER2_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B), + .raised = AVR_IO_REGBIT(TIFR2, OCF2B), + .vector = TIMER2_COMPB_vect, + }, + }, +}; + +static avr_t * make() +{ + return &mcu.core; +} + +avr_kind_t mega644 = { + .names = { "atmega644", "atmega644p" }, + .make = make +}; + +static void init(struct avr_t * avr) +{ + struct mcu_t * mcu = (struct mcu_t*)avr; + + printf("%s init\n", avr->mmcu); + + avr_eeprom_init(avr, &mcu->eeprom); + avr_ioport_init(avr, &mcu->porta); + avr_ioport_init(avr, &mcu->portb); + avr_ioport_init(avr, &mcu->portc); + avr_ioport_init(avr, &mcu->portd); + avr_uart_init(avr, &mcu->uart0); + avr_uart_init(avr, &mcu->uart1); + avr_timer8_init(avr, &mcu->timer0); + avr_timer8_init(avr, &mcu->timer2); +} + +static void reset(struct avr_t * avr) +{ +// struct mcu_t * mcu = (struct mcu_t*)avr; +} diff --git a/simavr/cores/sim_mega88.c b/simavr/cores/sim_mega88.c new file mode 100644 index 0000000..c5e43cb --- /dev/null +++ b/simavr/cores/sim_mega88.c @@ -0,0 +1,43 @@ +/* + sim_mega88.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "simavr.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "atmega88" +#define SIM_CORENAME mcu_mega88 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom88.h" +// instanciate the new core +#include "sim_megax8.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t mega88 = { + .names = { "atmega88", "atmega88p","atmega88pa" }, + .make = make +}; + diff --git a/simavr/cores/sim_megax8.c b/simavr/cores/sim_megax8.c new file mode 100644 index 0000000..44bf334 --- /dev/null +++ b/simavr/cores/sim_megax8.c @@ -0,0 +1,45 @@ +/* + sim_megax8.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ +#include +#include "simavr.h" + +#include "sim_megax8.h" + +void mx8_init(struct avr_t * avr) +{ + struct mcu_t * mcu = (struct mcu_t*)avr; + + printf("%s init\n", avr->mmcu); + + avr_eeprom_init(avr, &mcu->eeprom); + avr_ioport_init(avr, &mcu->portb); + avr_ioport_init(avr, &mcu->portc); + avr_ioport_init(avr, &mcu->portd); + avr_uart_init(avr, &mcu->uart); + avr_timer8_init(avr, &mcu->timer0); + avr_timer8_init(avr, &mcu->timer2); + avr_spi_init(avr, &mcu->spi); +} + +void mx8_reset(struct avr_t * avr) +{ +// struct mcu_t * mcu = (struct mcu_t*)avr; +} diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h new file mode 100644 index 0000000..cbe6de2 --- /dev/null +++ b/simavr/cores/sim_megax8.h @@ -0,0 +1,209 @@ +/* + sim_megax8.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + + +#ifndef __SIM_MEGAX8_H__ +#define __SIM_MEGAX8_H__ + +#include "sim_core_declare.h" +#include "avr_eeprom.h" +#include "avr_ioport.h" +#include "avr_uart.h" +#include "avr_timer8.h" +#include "avr_spi.h" + +void mx8_init(struct avr_t * avr); +void mx8_reset(struct avr_t * avr); + +/* + * This is a template for all of the x8 devices, hopefuly + */ +struct mcu_t { + avr_t core; + avr_eeprom_t eeprom; + avr_ioport_t portb,portc,portd; + avr_uart_t uart; + avr_timer8_t timer0,timer2; + avr_spi_t spi; +}; + +#ifdef SIM_CORENAME + +#ifndef SIM_VECTOR_SIZE +#error SIM_VECTOR_SIZE is not declared +#endif +#ifndef SIM_MMCU +#error SIM_MMCU is not declared +#endif + +struct mcu_t SIM_CORENAME = { + .core = { + .mmcu = SIM_MMCU, + DEFAULT_CORE(SIM_VECTOR_SIZE), + + .init = mx8_init, + .reset = mx8_reset, + }, + .eeprom = { + .size = E2END+1, + .r_eearh = EEARH, + .r_eearl = EEARL, + .r_eedr = EEDR, + .r_eecr = EECR, + .eepm = { AVR_IO_REGBIT(EECR, EEPM0), AVR_IO_REGBIT(EECR, EEPM1) }, + .eempe = AVR_IO_REGBIT(EECR, EEMPE), + .eepe = AVR_IO_REGBIT(EECR, EEPE), + .eere = AVR_IO_REGBIT(EECR, EERE), + .ready = { + .enable = AVR_IO_REGBIT(EECR, EERIE), + .vector = EE_READY_vect, + }, + }, + .portb = { + .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE0), + .raised = AVR_IO_REGBIT(PCIFR, PCIF0), + .vector = PCINT0_vect, + }, + .r_pcint = PCMSK0, + }, + .portc = { + .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE1), + .raised = AVR_IO_REGBIT(PCIFR, PCIF1), + .vector = PCINT1_vect, + }, + .r_pcint = PCMSK1, + }, + .portd = { + .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE2), + .raised = AVR_IO_REGBIT(PCIFR, PCIF2), + .vector = PCINT2_vect, + }, + .r_pcint = PCMSK2, + }, + + .uart = { + .disabled = AVR_IO_REGBIT(PRR,PRUSART0), + .name = '0', + .r_udr = UDR0, + .udre = AVR_IO_REGBIT(UCSR0A, UDRE0), + + .r_ucsra = UCSR0A, + .r_ucsrb = UCSR0B, + .r_ucsrc = UCSR0C, + .r_ubrrl = UBRR0L, + .r_ubrrh = UBRR0H, + .rxc = { + .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0), + .vector = USART_RX_vect, + }, + .txc = { + .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0), + .vector = USART_TX_vect, + }, + .udrc = { + .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0), + .vector = USART_UDRE_vect, + }, + }, + + .timer0 = { + .name = '0', + .disabled = AVR_IO_REGBIT(PRR,PRTIM0), + .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, + .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR0A, + .r_ocrb = OCR0B, + .r_tcnt = TCNT0, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK0, TOIE0), + .raised = AVR_IO_REGBIT(TIFR0, TOV0), + .vector = TIMER0_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A), + .raised = AVR_IO_REGBIT(TIFR0, OCF0A), + .vector = TIMER0_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B), + .raised = AVR_IO_REGBIT(TIFR0, OCF0B), + .vector = TIMER0_COMPB_vect, + }, + }, + .timer2 = { + .name = '2', + .disabled = AVR_IO_REGBIT(PRR,PRTIM2), + .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) }, + .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) }, + .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR2A, + .r_ocrb = OCR2B, + .r_tcnt = TCNT2, + + // asynchronous timer source bit.. if set, use 32khz frequency + .as2 = AVR_IO_REGBIT(ASSR, AS2), + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK2, TOIE2), + .raised = AVR_IO_REGBIT(TIFR2, TOV2), + .vector = TIMER2_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A), + .raised = AVR_IO_REGBIT(TIFR2, OCF2A), + .vector = TIMER2_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B), + .raised = AVR_IO_REGBIT(TIFR2, OCF2B), + .vector = TIMER2_COMPB_vect, + }, + }, + + .spi = { + .disabled = AVR_IO_REGBIT(PRR,PRSPI), + .spe = AVR_IO_REGBIT(SPCR, SPE), + .dord = AVR_IO_REGBIT(SPCR, DORD), + .mstr = AVR_IO_REGBIT(SPCR, MSTR), + .cpol = AVR_IO_REGBIT(SPCR, CPOL), + .cpha = AVR_IO_REGBIT(SPCR, CPHA), + + .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) }, + .spi = { + .enable = AVR_IO_REGBIT(SPCR, SPIE), + .raised = AVR_IO_REGBIT(SPSR, SPIF), + .vector = SPI_STC_vect, + }, + }, +}; +#endif /* SIM_CORENAME */ + +#endif /* __SIM_MEGAX8_H__ */ \ No newline at end of file diff --git a/simavr/cores/sim_tiny85.c b/simavr/cores/sim_tiny85.c new file mode 100644 index 0000000..850005c --- /dev/null +++ b/simavr/cores/sim_tiny85.c @@ -0,0 +1,155 @@ +/* + sim_tiny85.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "simavr.h" +#include "sim_core_declare.h" +#include "avr_eeprom.h" +#include "avr_ioport.h" +#include "avr_timer8.h" + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iotn85.h" + +static void init(struct avr_t * avr); +static void reset(struct avr_t * avr); + + +static struct mcu_t { + avr_t core; + avr_eeprom_t eeprom; + avr_ioport_t portb; + avr_timer8_t timer0, timer1; +} mcu = { + .core = { + .mmcu = "attiny85", + DEFAULT_CORE(2), + + .init = init, + .reset = reset, + }, + .eeprom = { + .size = E2END+1, + .r_eearh = EEARH, + .r_eearl = EEARL, + .r_eedr = EEDR, + .r_eecr = EECR, + .eepm = { AVR_IO_REGBIT(EECR, EEPM0), AVR_IO_REGBIT(EECR, EEPM1) }, + .eempe = AVR_IO_REGBIT(EECR, EEMPE), + .eepe = AVR_IO_REGBIT(EECR, EEPE), + .eere = AVR_IO_REGBIT(EECR, EERE), + .ready = { + .enable = AVR_IO_REGBIT(EECR, EERIE), + .vector = EE_RDY_vect,// EE_READY_vect, + }, + }, + .portb = { + .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, + .pcint = { + .enable = AVR_IO_REGBIT(GIMSK, PCIE), + .raised = AVR_IO_REGBIT(GIFR, PCIF), + .vector = PCINT0_vect, + }, + .r_pcint = PCMSK, + }, + .timer0 = { + .name = '0', + .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, + .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, + + .r_ocra = OCR0A, + .r_ocrb = OCR0B, + .r_tcnt = TCNT0, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE0), + .raised = AVR_IO_REGBIT(TIFR, TOV0), + .vector = TIMER0_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE0A), + .raised = AVR_IO_REGBIT(TIFR, OCF0A), + .vector = TIMER0_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE0B), + .raised = AVR_IO_REGBIT(TIFR, OCF0B), + .vector = TIMER0_COMPB_vect, + }, + }, + .timer1 = { + .name = '1', + // no wgm bits + .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) }, + .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ }, + + .r_ocra = OCR1A, + .r_ocrb = OCR1B, + .r_ocrc = OCR1C, + .r_tcnt = TCNT1, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE1), + .raised = AVR_IO_REGBIT(TIFR, TOV1), + .vector = TIMER1_OVF_vect, + }, + .compa = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1A), + .raised = AVR_IO_REGBIT(TIFR, OCF1A), + .vector = TIMER1_COMPA_vect, + }, + .compb = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1B), + .raised = AVR_IO_REGBIT(TIFR, OCF1B), + .vector = TIMER1_COMPB_vect, + }, + }, + + +}; + +static avr_t * make() +{ + return &mcu.core; +} + +avr_kind_t tiny85 = { + .make = make +}; + +static void init(struct avr_t * avr) +{ + struct mcu_t * mcu = (struct mcu_t*)avr; + + printf("%s init\n", avr->mmcu); + + avr_eeprom_init(avr, &mcu->eeprom); + avr_ioport_init(avr, &mcu->portb); + avr_timer8_init(avr, &mcu->timer0); + avr_timer8_init(avr, &mcu->timer1); +} + +static void reset(struct avr_t * avr) +{ +// struct mcu_t * mcu = (struct mcu_t*)avr; +} diff --git a/simavr/sim/avr_eeprom.c b/simavr/sim/avr_eeprom.c new file mode 100644 index 0000000..f7a2d60 --- /dev/null +++ b/simavr/sim/avr_eeprom.c @@ -0,0 +1,121 @@ +/* + avr_eeprom.c + + IO module that simulates the AVR EEProm + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include +#include +#include "avr_eeprom.h" + +static void avr_eeprom_run(avr_t * avr, avr_io_t * port) +{ + avr_eeprom_t * p = (avr_eeprom_t *)port; + //printf("%s\n", __FUNCTION__); + if (p->eempe_clear_timer) { + p->eempe_clear_timer--; + if (p->eempe_clear_timer == 0) { + avr_regbit_clear(avr, p->eempe); + } + } + if (p->ready_raise_timer) { + p->ready_raise_timer--; + if (p->ready_raise_timer == 0) { + avr_raise_interupt(avr, &p->ready); + } + } +} + +static void avr_eeprom_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param) +{ + avr_eeprom_t * p = (avr_eeprom_t *)param; + uint8_t eempe = avr_regbit_get(avr, p->eempe); + + avr_core_watch_write(avr, addr, v); + + if (!eempe && avr_regbit_get(avr, p->eempe)) { + p->eempe_clear_timer = 4; // auto clear, later + } + + if (eempe && avr_regbit_get(avr, p->eepe)) { // write operation + uint16_t addr = avr->data[p->r_eearl] | (avr->data[p->r_eearh] << 8); + printf("eeprom write %04x <- %02x\n", addr, avr->data[p->r_eedr]); + p->eeprom[addr] = avr->data[p->r_eedr]; + // automaticaly clears that bit (?) + p->eempe_clear_timer = 0; + avr_regbit_clear(avr, p->eempe); + + p->ready_raise_timer = 1024; // make a avr_milliseconds_to_cycle(...) 3.4ms here + } + if (avr_regbit_get(avr, p->eere)) { // read operation + uint16_t addr = avr->data[p->r_eearl] | (avr->data[p->r_eearh] << 8); + avr->data[p->r_eedr] = p->eeprom[addr]; + printf("eeprom read %04x : %02x\n", addr, p->eeprom[addr]); + } + + // autocleared + avr_regbit_clear(avr, p->eepe); + avr_regbit_clear(avr, p->eere); +} + +static int avr_eeprom_ioctl(avr_t * avr, avr_io_t * port, uint32_t ctl, void * io_param) +{ + avr_eeprom_t * p = (avr_eeprom_t *)port; + int res = -1; + + switch(ctl) { + case AVR_IOCTL_EEPROM_SET: { + avr_eeprom_desc_t * desc = (avr_eeprom_desc_t*)io_param; + if (!desc || !desc->size || !desc->ee || (desc->offset + desc->size) >= p->size) { + printf("%s: AVR_IOCTL_EEPROM_SET Invalid argument\n", + __FUNCTION__); + return -2; + } + memcpy(p->eeprom + desc->offset, desc->ee, desc->size); + printf("%s: AVR_IOCTL_EEPROM_SET Loaded %d at offset %d\n", + __FUNCTION__, desc->size, desc->offset); + } break; + } + + return res; +} + +static avr_io_t _io = { + .kind = "eeprom", + .run = avr_eeprom_run, + .ioctl = avr_eeprom_ioctl, +}; + +void avr_eeprom_init(avr_t * avr, avr_eeprom_t * p) +{ + p->io = _io; + printf("%s init (%d bytes) EEL/H:%02x/%02x EED=%02x EEC=%02x\n", + __FUNCTION__, p->size, p->r_eearl, p->r_eearh, p->r_eedr, p->r_eecr); + + p->eeprom = malloc(p->size); + memset(p->eeprom, 0xff, p->size); + + avr_register_io(avr, &p->io); + avr_register_vector(avr, &p->ready); + + avr_register_io_write(avr, p->r_eecr, avr_eeprom_write, p); +} + diff --git a/simavr/sim/avr_eeprom.h b/simavr/sim/avr_eeprom.h new file mode 100644 index 0000000..37585bf --- /dev/null +++ b/simavr/sim/avr_eeprom.h @@ -0,0 +1,61 @@ +/* + avr_eeprom.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __AVR_EEPROM_H__ +#define __AVR_EEPROM_H__ + +#include "simavr.h" + +typedef struct avr_eeprom_t { + avr_io_t io; + + uint8_t * eeprom; // actual bytes + uint16_t size; // size for this MCU + + uint8_t r_eearh; + uint8_t r_eearl; + uint8_t r_eedr; + + // eepm -- eeprom write mode + uint8_t r_eecr; // shortcut, assumes these bits fit in that register + avr_regbit_t eepm[4]; + avr_regbit_t eempe; // eeprom master program enable + avr_regbit_t eepe; // eeprom program enable + avr_regbit_t eere; // eeprom read enable + + avr_int_vector_t ready; // EERIE vector + + uint32_t eempe_clear_timer; + uint32_t ready_raise_timer; +} avr_eeprom_t; + +void avr_eeprom_init(avr_t * avr, avr_eeprom_t * port); + +typedef struct avr_eeprom_desc_t { + uint8_t * ee; + uint16_t offset; + uint32_t size; +} avr_eeprom_desc_t; + +#define AVR_IOCTL_EEPROM_GET AVR_IOCTL_DEF('e','e','g','p') +#define AVR_IOCTL_EEPROM_SET AVR_IOCTL_DEF('e','e','s','p') + +#endif /* __AVR_EEPROM_H__ */ diff --git a/simavr/sim/avr_ioport.c b/simavr/sim/avr_ioport.c new file mode 100644 index 0000000..157a624 --- /dev/null +++ b/simavr/sim/avr_ioport.c @@ -0,0 +1,102 @@ +/* + avr_ioport.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "avr_ioport.h" + +static void avr_ioport_run(avr_t * avr, avr_io_t * port) +{ + //printf("%s\n", __FUNCTION__); +} + +static uint8_t avr_ioport_read(struct avr_t * avr, uint8_t addr, void * param) +{ + avr_ioport_t * p = (avr_ioport_t *)param; + uint8_t v = avr->data[addr]; + + if (addr == p->r_pin) { + uint8_t v = avr->data[p->r_port]; + avr->data[addr] = v; + // made to trigger potential watchpoints + v = avr_core_watch_read(avr, addr); +// printf("** PIN%c(%02x) = %02x\n", p->name, addr, v); + } + return v; +} + +static void avr_ioport_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param) +{ + avr_ioport_t * p = (avr_ioport_t *)param; + uint8_t oldv = avr->data[addr]; + + if (addr == p->r_port) { + // printf("PORT%c(%02x) = %02x (was %02x)\n", p->name, addr, v, oldv); + + avr_core_watch_write(avr, addr, v); + if (v != oldv) { + int raise = 1; + int mask = v ^ oldv; + if (p->r_pcint) + raise = avr->data[p->r_pcint] & mask; + if (raise) + avr_raise_interupt(avr, &p->pcint); + } + + + if (p->name == 'D') { + static int cs = -1; + if ((oldv & 0xf0) != (v & 0xf0)) { + for (int i = 0; i < 4; i++) { + + } + } + { + } + } + } +} + +static void avr_ioport_reset(avr_t * avr, avr_io_t * port) +{ +} + +static avr_io_t _io = { + .kind = "io", + .run = avr_ioport_run, + .reset = avr_ioport_reset, +}; + +void avr_ioport_init(avr_t * avr, avr_ioport_t * port) +{ + port->io = _io; + printf("%s PIN%c 0x%02x DDR%c 0x%02x PORT%c 0x%02x\n", + __FUNCTION__, + port->name, port->r_pin, + port->name, port->r_ddr, + port->name, port->r_port); + + avr_register_io(avr, &port->io); + avr_register_vector(avr, &port->pcint); + + avr_register_io_write(avr, port->r_port, avr_ioport_write, port); + avr_register_io_read(avr, port->r_pin, avr_ioport_read, port); +} + diff --git a/simavr/sim/avr_ioport.h b/simavr/sim/avr_ioport.h new file mode 100644 index 0000000..9f38995 --- /dev/null +++ b/simavr/sim/avr_ioport.h @@ -0,0 +1,41 @@ +/* + avr_ioport.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __AVR_IOPORT_H__ +#define __AVR_IOPORT_H__ + +#include "simavr.h" + +typedef struct avr_ioport_t { + avr_io_t io; + char name; + uint8_t r_port; + uint8_t r_ddr; + uint8_t r_pin; + + avr_int_vector_t pcint; // PCINT vector + uint8_t r_pcint; // pcint 8 pins mask + +} avr_ioport_t; + +void avr_ioport_init(avr_t * avr, avr_ioport_t * port); + +#endif /* __AVR_IOPORT_H__ */ diff --git a/simavr/sim/avr_spi.c b/simavr/sim/avr_spi.c new file mode 100644 index 0000000..b373e8e --- /dev/null +++ b/simavr/sim/avr_spi.c @@ -0,0 +1,82 @@ +/* + avr_spi.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "avr_spi.h" + +static void avr_spi_run(avr_t * avr, avr_io_t * port) +{ +// printf("%s\n", __FUNCTION__); +} + +#if 0 +static uint8_t avr_spi_read(struct avr_t * avr, uint8_t addr, void * param) +{ + avr_spi_t * p = (avr_spi_t *)param; + uint8_t v = avr->data[addr]; +// printf("** PIN%c = %02x\n", p->name, v); + return v; +} + +static void avr_spi_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param) +{ + avr_spi_t * p = (avr_spi_t *)param; + + if (addr == p->r_udr) { + // printf("UDR%c(%02x) = %02x\n", p->name, addr, v); + avr_core_watch_write(avr, addr, v); + avr_regbit_set(avr, p->udre); + + static char buf[128]; + static int l = 0; + buf[l++] = v <= ' ' ? '.' : v; + buf[l] = 0; + if (v == '\n' || l == 127) { + l = 0; + printf("\e[32m%s\e[0m\n", buf); + } + } +} +#endif + +void avr_spi_reset(avr_t * avr, struct avr_io_t *io) +{ +// avr_spi_t * p = (avr_spi_t *)io; +// avr_regbit_set(avr, p->udre); +} + +static avr_io_t _io = { + .kind = "spi", + .run = avr_spi_run, + .reset = avr_spi_reset, +}; + +void avr_spi_init(avr_t * avr, avr_spi_t * p) +{ + p->io = _io; + avr_register_io(avr, &p->io); + + printf("%s SPI%c init\n", __FUNCTION__, p->name); + +// avr_register_io_write(avr, p->r_udr, avr_spi_write, p); +// avr_register_io_read(avr, p->r_udr, avr_spi_read, p); +} + diff --git a/simavr/sim/avr_spi.h b/simavr/sim/avr_spi.h new file mode 100644 index 0000000..0cae169 --- /dev/null +++ b/simavr/sim/avr_spi.h @@ -0,0 +1,47 @@ +/* + avr_spi.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef AVR_SPI_H_ +#define AVR_SPI_H_ + +#include "simavr.h" + +typedef struct avr_spi_t { + avr_io_t io; + char name; + avr_regbit_t disabled; // bit in the PRR + + uint8_t r_spdr; // data register + uint8_t r_spcr; // control register + + avr_regbit_t spe; // spi enable + avr_regbit_t dord; // data order + avr_regbit_t mstr; // master/slave + avr_regbit_t cpol; // clock polarity + avr_regbit_t cpha; // phase + avr_regbit_t spr[4]; // clock divider + + avr_int_vector_t spi; // spi interupt +} avr_spi_t; + +void avr_spi_init(avr_t * avr, avr_spi_t * port); + +#endif /* AVR_SPI_H_ */ diff --git a/simavr/sim/avr_timer8.c b/simavr/sim/avr_timer8.c new file mode 100644 index 0000000..93bcb9c --- /dev/null +++ b/simavr/sim/avr_timer8.c @@ -0,0 +1,118 @@ +/* + avr_timer8.c + + Handles the just one mode of the 8 bit AVR timer. + Still need to handle all the others! + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "avr_timer8.h" + +static void avr_timer8_run(avr_t * avr, avr_io_t * port) +{ + avr_timer8_t * p = (avr_timer8_t *)port; + //printf("%s\n", __FUNCTION__); + + if (p->compa_cycles) { + if (p->compa_next == 0) { + p->compa_next = avr->cycle + p->compa_cycles; + } + if (avr->cycle >= p->compa_next) { + // printf("timer a firea %d\n", p->compa_next); + fflush(stdout); + p->compa_next += p->compa_cycles; + avr_raise_interupt(avr, &p->compa); + } + } +} + +#if 0 +static uint8_t avr_timer8_read(struct avr_t * avr, uint8_t addr, void * param) +{ + avr_timer8_t * p = (avr_timer8_t *)param; + uint8_t v = avr->data[addr]; + + if (addr == p->r_pin) { + uint8_t v = avr->data[p->r_port]; + avr->data[addr] = v; + // made to trigger potential watchpoints + v = avr_core_watch_read(avr, addr); + printf("** PIN%c(%02x) = %02x\n", p->name, addr, v); + } + return v; +} +#endif + +static void avr_timer8_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param) +{ + avr_timer8_t * p = (avr_timer8_t *)param; +// uint8_t oldv = avr->data[addr]; + + p->compa_cycles = 0; + p->compa_next = 0; + + avr_core_watch_write(avr, addr, v); + long clock = avr->frequency; + if (avr_regbit_get(avr, p->as2)) + clock = 32768; + uint8_t cs = avr_regbit_get_array(avr, p->cs, ARRAY_SIZE(p->cs)); + if (cs == 0) { + printf("%s-%c clock turned off\n", __FUNCTION__, p->name); + } + uint8_t mode = avr_regbit_get_array(avr, p->wgm, ARRAY_SIZE(p->wgm)); + uint8_t cs_div = p->cs_div[cs]; + uint16_t ocra = avr->data[p->r_ocra]; + uint16_t ocrb = avr->data[p->r_ocrb]; + long f = clock >> cs_div; + long fa = f / 2 / (ocra+1), fb = f / 2 / (ocrb+1); + + printf("%s-%c clock f=%ld cs=%02x (div %d) = %ldhz\n", __FUNCTION__, p->name, clock, cs, 1 << cs_div, f); + printf("%s-%c wgm %d OCRA=%3d = %ldhz\n", __FUNCTION__, p->name, mode, ocra, fa); + printf("%s-%c wgm %d OCRB=%3d = %ldhz\n", __FUNCTION__, p->name, mode, ocrb, fb); + + long cocra = ocra ? avr->frequency / fa : 0; + p->compa_cycles = cocra; + printf("%s-%c A %ld/%ld = cycles = %ld\n", __FUNCTION__, p->name, (long)avr->frequency, fa, cocra); + +} + +static void avr_timer8_reset(avr_t * avr, avr_io_t * port) +{ +} + +static avr_io_t _io = { + .kind = "timer8", + .run = avr_timer8_run, + .reset = avr_timer8_reset, +}; + +void avr_timer8_init(avr_t * avr, avr_timer8_t * p) +{ + p->io = _io; + printf("%s timer%c created\n", __FUNCTION__, p->name); + + avr_register_io(avr, &p->io); +// avr_register_vector(avr, &port->pcint); + + avr_register_io_write(avr, p->cs[0].reg, avr_timer8_write, p); + avr_register_io_write(avr, p->r_ocra, avr_timer8_write, p); + avr_register_io_write(avr, p->r_ocrb, avr_timer8_write, p); + //avr_register_io_read(avr, port->r_pin, avr_ioport_read, port); +} diff --git a/simavr/sim/avr_timer8.h b/simavr/sim/avr_timer8.h new file mode 100644 index 0000000..b73a831 --- /dev/null +++ b/simavr/sim/avr_timer8.h @@ -0,0 +1,49 @@ +/* + avr_timer8.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef AVR_TIMER8_H_ +#define AVR_TIMER8_H_ + +#include "simavr.h" + +typedef struct avr_timer8_t { + avr_io_t io; + char name; + avr_regbit_t disabled; // bit in the PRR + + uint8_t r_ocra, r_ocrb, r_ocrc, r_tcnt; + + avr_regbit_t wgm[4]; + avr_regbit_t cs[4]; + uint8_t cs_div[16]; + avr_regbit_t as2; // asynchronous clock 32khz + + avr_int_vector_t compa; // comparator A + avr_int_vector_t compb; // comparator A + avr_int_vector_t overflow; // overflow + + + uint64_t compa_cycles, compa_next; +} avr_timer8_t; + +void avr_timer8_init(avr_t * avr, avr_timer8_t * port); + +#endif /* AVR_TIMER8_H_ */ diff --git a/simavr/sim/avr_uart.c b/simavr/sim/avr_uart.c new file mode 100644 index 0000000..06aca7a --- /dev/null +++ b/simavr/sim/avr_uart.c @@ -0,0 +1,85 @@ +/* + avr_uart.c + + Handles UART access + Right now just handle "write" to the serial port at any speed + and printf to the console when '\n' is written. + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "avr_uart.h" + +static void avr_uart_run(avr_t * avr, avr_io_t * port) +{ +// printf("%s\n", __FUNCTION__); +} + +static uint8_t avr_uart_read(struct avr_t * avr, uint8_t addr, void * param) +{ +// avr_uart_t * p = (avr_uart_t *)param; + uint8_t v = avr->data[addr]; +// printf("** PIN%c = %02x\n", p->name, v); + return v; +} + +static void avr_uart_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param) +{ + avr_uart_t * p = (avr_uart_t *)param; + + if (addr == p->r_udr) { + // printf("UDR%c(%02x) = %02x\n", p->name, addr, v); + avr_core_watch_write(avr, addr, v); + avr_regbit_set(avr, p->udre); + + static char buf[128]; + static int l = 0; + buf[l++] = v < ' ' ? '.' : v; + buf[l] = 0; + if (v == '\n' || l == 127) { + l = 0; + printf("\e[32m%s\e[0m\n", buf); + } + } +} + +void avr_uart_reset(avr_t * avr, struct avr_io_t *io) +{ + avr_uart_t * p = (avr_uart_t *)io; + avr_regbit_set(avr, p->udre); +} + +static avr_io_t _io = { + .kind = "uart", + .run = avr_uart_run, + .reset = avr_uart_reset, +}; + +void avr_uart_init(avr_t * avr, avr_uart_t * p) +{ + p->io = _io; + avr_register_io(avr, &p->io); + + printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr); + + avr_register_io_write(avr, p->r_udr, avr_uart_write, p); + avr_register_io_read(avr, p->r_udr, avr_uart_read, p); + +} + diff --git a/simavr/sim/avr_uart.h b/simavr/sim/avr_uart.h new file mode 100644 index 0000000..7ac6092 --- /dev/null +++ b/simavr/sim/avr_uart.h @@ -0,0 +1,49 @@ +/* + avr_uart.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef AVR_UART_H_ +#define AVR_UART_H_ + +#include "simavr.h" + +typedef struct avr_uart_t { + avr_io_t io; + char name; + avr_regbit_t disabled; // bit in the PRR + + uint8_t r_udr; + uint8_t r_ucsra; + uint8_t r_ucsrb; + uint8_t r_ucsrc; + + uint8_t r_ubrrl,r_ubrrh; + + avr_int_vector_t rxc; + avr_int_vector_t txc; + avr_int_vector_t udrc; + + avr_regbit_t udre; // AVR_IO_REGBIT(UCSR0A, UDRE0), + +} avr_uart_t; + +void avr_uart_init(avr_t * avr, avr_uart_t * port); + +#endif /* AVR_UART_H_ */ diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c new file mode 100644 index 0000000..53271e1 --- /dev/null +++ b/simavr/sim/sim_core.c @@ -0,0 +1,1129 @@ +/* + sim_core.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include +#include +#include +#include "simavr.h" +#include "sim_core.h" + +// SREG bit names +const char * _sreg_bit_name = "cznvshti"; + +/* + * Handle "touching" registers, marking them changed. + * This is used only for debugging purposes to be able to + * print the effects of each instructions on registers + */ +#define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f)) +#define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f))) + +/* + * This allows a "special case" to skip indtruction tracing when in these + * symbols. since printf() is useful to have, but generates a lot of cycles + */ +int dont_trace(const char * name) +{ + return ( + !strcmp(name, "uart_putchar") || + !strcmp(name, "fputc") || + !strcmp(name, "printf") || + !strcmp(name, "vfprintf") || + !strcmp(name, "__ultoa_invert") || + !strcmp(name, "__prologue_saves__") || + !strcmp(name, "__epilogue_restores__")); +} + +int donttrace = 0; + +#define STATE(_f, args...) { \ + if (avr->trace) {\ + if (avr->codeline[avr->pc>>1]) {\ + const char * symn = avr->codeline[avr->pc>>1]->symbol; \ + int dont = 0 && dont_trace(symn);\ + if (dont!=donttrace) { \ + donttrace = dont;\ + DUMP_REG();\ + }\ + if (donttrace==0)\ + printf("%04x: %-25s " _f, avr->pc, symn, ## args);\ + } else \ + printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\ + }\ + } +#define SREG() if (avr->trace && donttrace == 0) {\ + printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \ + for (int _sbi = 0; _sbi < 8; _sbi++)\ + printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\ + printf("\n");\ +} + +/* + * Set a register (r < 256) + * if it's an IO regisrer (> 31) also (try to) call any callback that was + * registered to track changes to that register. + */ +static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v) +{ + REG_TOUCH(avr, r); + + if (r == R_SREG) { + avr->data[r] = v; + // unsplit the SREG + for (int i = 0; i < 8; i++) + avr->sreg[i] = (avr->data[R_SREG] & (1 << i)) != 0; + SREG(); + } + if (r > 31) { + uint8_t io = AVR_DATA_TO_IO(r); + if (avr->iow[io].w) + avr->iow[io].w(avr, r, v, avr->iow[io].param); + else + avr->data[r] = v; + } else + avr->data[r] = v; +} + +/* + * Stack pointer access + */ +inline uint16_t _avr_sp_get(avr_t * avr) +{ + return avr->data[R_SPL] | (avr->data[R_SPH] << 8); +} + +inline void _avr_sp_set(avr_t * avr, uint16_t sp) +{ + _avr_set_r(avr, R_SPL, sp); + _avr_set_r(avr, R_SPH, sp >> 8); +} + +/* + * Set any address to a value; split between registers and SRAM + */ +static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v) +{ + if (addr < 256) + _avr_set_r(avr, addr, v); + else + avr_core_watch_write(avr, addr, v); +} + +/* + * Get a value from SRAM. + */ +static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr) +{ + if (addr > 31 && addr < 256) { + uint8_t io = AVR_DATA_TO_IO(addr); + if (avr->ior[io].r) + avr->data[addr] = avr->ior[io].r(avr, addr, avr->ior[io].param); + } + return avr_core_watch_read(avr, addr); +} + +/* + * Stack oush accessors. Push/pop 8 and 16 bits + */ +static inline void _avr_push8(avr_t * avr, uint16_t v) +{ + uint16_t sp = _avr_sp_get(avr); + _avr_set_ram(avr, sp, v); + _avr_sp_set(avr, sp-1); +} + +static inline uint8_t _avr_pop8(avr_t * avr) +{ + uint16_t sp = _avr_sp_get(avr) + 1; + uint8_t res = _avr_get_ram(avr, sp); + _avr_sp_set(avr, sp); + return res; +} + +inline void _avr_push16(avr_t * avr, uint16_t v) +{ + _avr_push8(avr, v >> 8); + _avr_push8(avr, v); +} + +static inline uint16_t _avr_pop16(avr_t * avr) +{ + uint16_t res = _avr_pop8(avr); + res |= _avr_pop8(avr) << 8; + return res; +} + +/* + * "Pretty" register names + */ +const char * reg_names[255] = { + [R_XH] = "XH", [R_XL] = "XL", + [R_YH] = "YH", [R_YL] = "YL", + [R_ZH] = "ZH", [R_ZL] = "ZL", + [R_SPH] = "SPH", [R_SPL] = "SPL", + [R_SREG] = "SREG", +}; + + +const char * avr_regname(uint8_t reg) +{ + if (!reg_names[reg]) { + char tt[16]; + if (reg < 32) + sprintf(tt, "r%d", reg); + else + sprintf(tt, "io:%02x", reg); + reg_names[reg] = strdup(tt); + } + return reg_names[reg]; +} + +/* + * Called when an invalid opcode is decoded + */ +static void _avr_invalid_opcode(avr_t * avr) +{ + printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n", + avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8)); +} + +/* + * Dump changed registers when tracing + */ +void avr_dump_state(avr_t * avr) +{ + if (!avr->trace || donttrace) + return; + + int doit = 0; + + for (int r = 0; r < 3 && !doit; r++) + if (avr->touched[r]) + doit = 1; + if (!doit) + return; + printf(" ->> "); + const int r16[] = { R_SPL, R_XL, R_YL, R_ZL }; + for (int i = 0; i < 4; i++) + if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) { + REG_TOUCH(avr, r16[i]); + REG_TOUCH(avr, r16[i]+1); + } + + for (int i = 0; i < 3*32; i++) + if (REG_ISTOUCHED(avr, i)) { + printf("%s=%02x ", avr_regname(i), avr->data[i]); + } + printf("\n"); +} + +#define get_r_d_10(o) \ + const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \ + const uint8_t d = (o >> 4) & 0x1f;\ + const uint8_t vd = avr->data[d], vr =avr->data[r]; +#define get_k_r16(o) \ + const uint8_t r = 16 + ((o >> 4) & 0xf); \ + const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf); + +/* + * Add a "jump" address to the jump trace buffer + */ +#define TRACE_JUMP()\ + avr->old[avr->old_pci].pc = avr->pc;\ + avr->old[avr->old_pci].sp = _avr_sp_get(avr);\ + avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\ + +/****************************************************************************\ + * + * Helper functions for calculating the status register bit values. + * See the Atmel data sheet for the instuction set for more info. + * +\****************************************************************************/ + +static uint8_t +get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) +{ + uint8_t resb = res >> b & 0x1; + uint8_t rdb = rd >> b & 0x1; + uint8_t rrb = rr >> b & 0x1; + return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb); +} + +static uint8_t +get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr) +{ + uint8_t res7 = res >> 7 & 0x1; + uint8_t rd7 = rd >> 7 & 0x1; + uint8_t rr7 = rr >> 7 & 0x1; + return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7); +} + +static uint8_t +get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) +{ + uint8_t resb = res >> b & 0x1; + uint8_t rdb = rd >> b & 0x1; + uint8_t rrb = rr >> b & 0x1; + return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb); +} + +static uint8_t +get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr) +{ + uint8_t res7 = res >> 7 & 0x1; + uint8_t rd7 = rd >> 7 & 0x1; + uint8_t rr7 = rr >> 7 & 0x1; + return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7); +} + +static uint8_t +get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) +{ + uint8_t resb = (res >> b) & 0x1; + uint8_t rdb = (rd >> b) & 0x1; + uint8_t rrb = (rr >> b) & 0x1; + return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb); +} + +static uint8_t +get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr) +{ + res >>= 7; rd >>= 7; rr >>= 7; + /* The atmel data sheet says the second term is ~rd7 for CP + * but that doesn't make any sense. You be the judge. */ + return (rd & ~rr & ~res) | (~rd & rr & res); +} + +/* + * Main opcode decoder + * + * The decoder was written by following the datasheet in no particular order. + * As I went along, I noticed "bit patterns" that could be used to factor opcodes + * However, a lot of these only becane apparent later on, so SOME instructions + * (skip of bit set etc) are compact, and some could use some refactoring (the ALU + * ones scream to be factored). + * I assume that the decoder could easily be 2/3 of it's current size. + * + * The core 'almost' work. There is a case where it munches the stack, problem to be + * debugged. + * + * It lacks a couple of multiply instructions, and the "extended" XMega jumps. + * + * for now all instructions take "one" cycle, the cycle+= needs to be added. + */ +uint16_t avr_run_one(avr_t * avr) +{ + /* + * this traces spurious reset or bad jump/opcodes and dumps the last 32 "jumps" to track it down + */ + if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) { + avr->trace = 1; + STATE("RESET\n"); + CRASH(); + } + + uint32_t opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc]; + uint32_t new_pc = avr->pc + 2; // future "default" pc + int cycle = 1; + + avr->touched[0] = avr->touched[1] = avr->touched[2] = 0; + + switch (opcode & 0xf000) { + case 0x0000: { + switch (opcode) { + case 0x0000: { // NOP + STATE("nop\n"); + } break; + default: { + switch (opcode & 0xfc00) { + case 0x0400: { // CPC compare with carry 0000 01rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd - vr - avr->sreg[S_C]; + STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + if (res) + avr->sreg[S_Z] = 0; + avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_compare_overflow(res, vd, vr); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x0c00: { // ADD without carry 0000 11 rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd + vr; + if (r == d) { + STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff); + } else { + STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + } + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_H] = get_add_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_add_overflow(res, vd, vr); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_add_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x0800: { // SBC substract with carry 0000 10rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd - vr - avr->sreg[S_C]; + STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res); + _avr_set_r(avr, d, res); + if (res) + avr->sreg[S_Z] = 0; + avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_sub_overflow(res, vd, vr); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + default: + switch (opcode & 0xff00) { + case 0x0100: { // MOVW – Copy Register Word 0000 0001 dddd rrrr + uint8_t d = ((opcode >> 4) & 0xf) << 1; + uint8_t r = ((opcode) & 0xf) << 1; + STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]); + _avr_set_r(avr, d, avr->data[r]); + _avr_set_r(avr, d+1, avr->data[r+1]); + } break; + default: _avr_invalid_opcode(avr); + } + } + } + } + } break; + + case 0x1000: { + switch (opcode & 0xfc00) { + case 0x1800: { // SUB without carry 0000 10 rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd - vr; + STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_sub_overflow(res, vd, vr); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x1000: { // CPSE Compare, skip if equal 0000 10 rd dddd rrrr + get_r_d_10(opcode); + uint16_t res = vd == vr; + STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not "); + if (res) + new_pc += 2; + } break; + case 0x1400: { // CP Compare 0000 10 rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd - vr; + STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_compare_overflow(res, vd, vr); + avr->sreg[S_N] = res >> 7; + avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x1c00: { // ADD with carry 0001 11 rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd + vr + avr->sreg[S_C]; + if (r == d) { + STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res); + } else { + STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res); + } + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_H] = get_add_carry(res, vd, vr, 3); + avr->sreg[S_V] = get_add_overflow(res, vd, vr); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_add_carry(res, vd, vr, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + default: + switch (opcode & 0xff00) { + case 0x0200: { // MULS – Multiply Signed 0000 0010 dddd rrrr + int8_t r = opcode & 0xf; + int8_t d = (opcode >> 4) & 0xf; + int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]); + STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res); + _avr_set_r(avr, 0, res); + _avr_set_r(avr, 1, res >> 8); + avr->sreg[S_C] = (res >> 15) & 1; + avr->sreg[S_Z] = res == 0; + SREG(); + } break; + default: _avr_invalid_opcode(avr); + } + } + } break; + + case 0x2000: { + switch (opcode & 0xfc00) { + case 0x2000: { // AND 0010 00rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd & vr; + if (r == d) { + STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]); + } else { + STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + } + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_V] = 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x2400: { // EOR 0010 01rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd ^ vr; + if (r==d) { + STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]); + } else { + STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + } + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_V] = 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x2800: { // OR Logical OR 0010 10rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vd | vr; + STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + _avr_set_r(avr, d, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_V] = 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x2c00: { // MOV 0010 11rd dddd rrrr + get_r_d_10(opcode); + uint8_t res = vr; + STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res); + _avr_set_r(avr, d, res); + } break; + default: _avr_invalid_opcode(avr); + } + } break; + + case 0x3000: { // CPI 0011 KKKK rrrr KKKK + get_k_r16(opcode); + uint8_t vr = avr->data[r]; + uint8_t res = vr - k; + STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k); + + avr->sreg[S_Z] = res == 0; + avr->sreg[S_H] = get_compare_carry(res, vr, k, 3); + avr->sreg[S_V] = get_compare_overflow(res, vr, k); + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = get_compare_carry(res, vr, k, 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + + case 0x4000: { // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk + get_k_r16(opcode); + uint8_t vr = avr->data[r]; + uint8_t res = vr - k - avr->sreg[S_C]; + STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + + case 0x5000: { // SUB Subtract Immediate 0101 10 kkkk dddd kkkk + get_k_r16(opcode); + uint8_t vr = avr->data[r]; + uint8_t res = vr - k; + STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_C] = k > vr; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + + case 0x6000: { // ORI aka SBR Logical AND with Immediate 0110 kkkk dddd kkkk + get_k_r16(opcode); + uint8_t res = avr->data[r] | k; + STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_V] = 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + + case 0x7000: { // ANDI Logical AND with Immediate 0111 kkkk dddd kkkk + get_k_r16(opcode); + uint8_t res = avr->data[r] & k; + STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = (res >> 7) & 1; + avr->sreg[S_V] = 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + + case 0xa000: + case 0x8000: { + switch (opcode & 0xd008) { + case 0xa000: + case 0x8000: { // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq + uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t q = ((opcode & 0x2000) >> 7) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7); + + if (opcode & 0x0200) { + STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]); + _avr_set_ram(avr, v+q, avr->data[r]); + } else { + STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]); + _avr_set_r(avr, r, _avr_get_ram(avr, v+q)); + } + } break; + case 0xa008: + case 0x8008: { // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq + uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8); + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t q = ((opcode & 0x2000) >> 7) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7); + + if (opcode & 0x0200) { + STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]); + _avr_set_ram(avr, v+q, avr->data[r]); + } else { + STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]); + _avr_set_r(avr, r, _avr_get_ram(avr, v+q)); + } + } break; + default: _avr_invalid_opcode(avr); + } + } break; + + case 0x9000: { + /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */ + if ((opcode & 0xff0f) == 0x9408) { + uint8_t b = (opcode >> 4) & 7; + STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]); + avr->sreg[b] = (opcode & 0x0080) == 0; + SREG(); + } else switch (opcode) { + case 0x9588: { // SLEEP + STATE("sleep\n"); + avr->state = cpu_Sleeping; + } break; + case 0x9598: { // BREAK + STATE("break\n"); + } break; + case 0x95a8: { // WDR + STATE("wdr\n"); + } break; + case 0x9409: { // IJMP Indirect jump + uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + STATE("ijmp Z[%04x]\n", z << 1); + new_pc = z << 1; + TRACE_JUMP(); + } break; + case 0x9509: { // ICALL Indirect Call to Subroutine + uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + STATE("icall Z[%04x]\n", z << 1); + + _avr_push16(avr, new_pc >> 1); + new_pc = z << 1; + TRACE_JUMP(); + } break; + case 0x9518: // RETI + case 0x9508: { // RET + new_pc = _avr_pop16(avr) << 1; + if (opcode & 0x10) // reti + avr->sreg[S_I] = 1; + STATE("ret%s\n", opcode & 0x10 ? "i" : ""); + TRACE_JUMP(); + } break; + case 0x95c8: { // LPM Load Program Memory R0 <- (Z) + uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z); + _avr_set_r(avr, 0, avr->flash[z]); + } break; + case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468: + case 0x9478: + { // BSET 1001 0100 0ddd 1000 + uint8_t b = (opcode >> 4) & 7; + avr->sreg[b] = 1; + STATE("bset %c\n", _sreg_bit_name[b]); + SREG(); + } break; + case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8: + case 0x94f8: + { // BSET 1001 0100 0ddd 1000 + uint8_t b = (opcode >> 4) & 7; + avr->sreg[b] = 0; + STATE("bclr %c\n", _sreg_bit_name[b]); + SREG(); + } break; + default: { + switch (opcode & 0xfe0f) { + case 0x9005: + case 0x9004: { // LPM Load Program Memory 1001 000d dddd 01oo + uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + uint8_t r = (opcode >> 4) & 0x1f; + int op = opcode & 3; + STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":""); + _avr_set_r(avr, r, avr->flash[z]); + if (op == 1) { + z++; + _avr_set_r(avr, R_ZH, z >> 8); + _avr_set_r(avr, R_ZL, z); + } + } break; + case 0x900c: + case 0x900d: + case 0x900e: { // LD Load Indirect from Data using X 1001 000r rrrr 11oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL]; + STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : ""); + + if (op == 2) x--; + _avr_set_r(avr, r, _avr_get_ram(avr, x)); + if (op == 1) x++; + _avr_set_r(avr, R_XH, x >> 8); + _avr_set_r(avr, R_XL, x); + } break; + case 0x920c: + case 0x920d: + case 0x920e: { // ST Store Indirect Data Space X 1001 001r rrrr 11oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL]; + STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]); + + if (op == 2) x--; + _avr_set_ram(avr, x, avr->data[r]); + if (op == 1) x++; + _avr_set_r(avr, R_XH, x >> 8); + _avr_set_r(avr, R_XL, x); + } break; + case 0x9009: + case 0x900a: { // LD Load Indirect from Data using Y 1001 000r rrrr 10oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL]; + STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : ""); + + if (op == 2) y--; + _avr_set_r(avr, r, _avr_get_ram(avr, y)); + if (op == 1) y++; + _avr_set_r(avr, R_YH, y >> 8); + _avr_set_r(avr, R_YL, y); + } break; + case 0x9209: + case 0x920a: { // ST Store Indirect Data Space Y 1001 001r rrrr 10oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL]; + STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]); + + if (op == 2) y--; + _avr_set_ram(avr, y, avr->data[r]); + if (op == 1) y++; + _avr_set_r(avr, R_YH, y >> 8); + _avr_set_r(avr, R_YL, y); + } break; + case 0x9200: { // STS ! Store Direct to Data Space, 32 bits + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc]; + new_pc += 2; + STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]); + _avr_set_ram(avr, x, avr->data[r]); + } break; + case 0x9001: + case 0x9002: { // LD Load Indirect from Data using Z 1001 001r rrrr 00oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL]; + STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : ""); + + if (op == 2) z--; + _avr_set_r(avr, r, _avr_get_ram(avr, z)); + if (op == 1) z++; + _avr_set_r(avr, R_ZH, z >> 8); + _avr_set_r(avr, R_ZL, z); + } break; + case 0x9201: + case 0x9202: { // ST Store Indirect Data Space Z 1001 001r rrrr 00oo + int op = opcode & 3; + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL]; + STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]); + + if (op == 2) z--; + _avr_set_ram(avr, z, avr->data[r]); + if (op == 1) z++; + _avr_set_r(avr, R_ZH, z >> 8); + _avr_set_r(avr, R_ZL, z); + } break; + case 0x900f: { // POP 1001 000d dddd 1111 + uint8_t r = (opcode >> 4) & 0x1f; + _avr_set_r(avr, r, _avr_pop8(avr)); + uint16_t sp = _avr_sp_get(avr); + STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]); + } break; + case 0x920f: { // PUSH 1001 001d dddd 1111 + uint8_t r = (opcode >> 4) & 0x1f; + _avr_push8(avr, avr->data[r]); + uint16_t sp = _avr_sp_get(avr); + STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp); + } break; + case 0x9000: { // LDS Load Direct from Data Space, 32 bits + uint8_t r = (opcode >> 4) & 0x1f; + uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc]; + new_pc += 2; + STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x); + _avr_set_r(avr, r, _avr_get_ram(avr, x)); + } break; + case 0x9400: { // COM – One’s Complement + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t res = 0xff - avr->data[r]; + STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = res >> 7; + avr->sreg[S_V] = 0; + avr->sreg[S_C] = 1; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x9401: { // NEG – One’s Complement + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t rd = avr->data[r]; + uint8_t res = 0x00 - rd; + STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res); + _avr_set_r(avr, r, res); + avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1; + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = res >> 7; + avr->sreg[S_V] = res == 0x80; + avr->sreg[S_C] = res != 0; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x9402: { // SWAP – Swap Nibbles + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ; + STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res); + _avr_set_r(avr, r, res); + } break; + case 0x9403: { // INC – Increment + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t res = avr->data[r] + 1; + STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = res >> 7; + avr->sreg[S_V] = res == 0x7f; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x9405: { // ASR – Arithmetic Shift Right 1001 010d dddd 0101 + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t vr = avr->data[r]; + uint8_t res = (vr >> 1) | (vr & 0x80); + STATE("asr %s[%02x]\n", avr_regname(r), vr); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_C] = vr & 1; + avr->sreg[S_N] = res >> 7; + avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C]; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x9406: { // LSR 1001 010d dddd 0110 + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t vr = avr->data[r]; + uint8_t res = vr >> 1; + STATE("lsr %s[%02x]\n", avr_regname(r), vr); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_C] = vr & 1; + avr->sreg[S_N] = 0; + avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C]; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x9407: { // ROR 1001 010d dddd 0111 + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t vr = avr->data[r]; + uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1; + STATE("ror %s[%02x]\n", avr_regname(r), vr); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_C] = vr & 1; + avr->sreg[S_N] = 0; + avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C]; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x940a: { // DEC – Decrement + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t res = avr->data[r] - 1; + STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res); + _avr_set_r(avr, r, res); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_N] = res >> 7; + avr->sreg[S_V] = res == 0x80; + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + } break; + case 0x940c: + case 0x940d: { // JMP Long Call to sub, 32 bits + uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1); + uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc]; + a = (a << 16) | x; + // printf("jmp %06x\n", a << 1); + STATE("jmp 0x%06x\n", a); + new_pc = a << 1; + TRACE_JUMP(); + } break; + case 0x940e: + case 0x940f: { // CALL Long Call to sub, 32 bits + uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1); + uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc]; + a = (a << 16) | x; + // printf("call %06x\n", a << 1); + STATE("call 0x%06x\n", a); + new_pc += 2; + _avr_push16(avr, new_pc >> 1); + new_pc = a << 1; + TRACE_JUMP(); + } break; + + default: { + switch (opcode & 0xff00) { + case 0x9600: { // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK + uint8_t r = 24 + ((opcode >> 3) & 0x6); + uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf); + uint8_t rdl = avr->data[r], rdh = avr->data[r+1]; + uint32_t res = rdl | (rdh << 8); + STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k); + res += k; + _avr_set_r(avr, r + 1, res >> 8); + _avr_set_r(avr, r, res); + avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1); + avr->sreg[S_Z] = (res & 0xffff) == 0; + avr->sreg[S_N] = (res >> 15) & 1; + avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + cycle++; + } break; + case 0x9700: { // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK + uint8_t r = 24 + ((opcode >> 3) & 0x6); + uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf); + uint8_t rdl = avr->data[r], rdh = avr->data[r+1]; + uint32_t res = rdl | (rdh << 8); + STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k); + res -= k; + _avr_set_r(avr, r + 1, res >> 8); + _avr_set_r(avr, r, res); + avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1); + avr->sreg[S_Z] = (res & 0xffff) == 0; + avr->sreg[S_N] = (res >> 15) & 1; + avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7); + avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V]; + SREG(); + cycle++; + } break; + case 0x9800: { // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb + uint8_t io = ((opcode >> 3) & 0x1f) + 32; + uint8_t b = opcode & 0x7; + uint8_t res = _avr_get_ram(avr, io) & ~(1 << b); + STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<> 3) & 0x1f) + 32; + uint8_t b = opcode & 0x7; + uint8_t res = _avr_get_ram(avr, io) & (1 << b); + STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<> 3) & 0x1f) + 32; + uint8_t b = opcode & 0x7; + uint8_t res = _avr_get_ram(avr, io) | (1 << b); + STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<> 3) & 0x1f; + uint8_t b = opcode & 0x7; + uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b); + STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<> 8); + avr->sreg[S_Z] = res == 0; + avr->sreg[S_C] = (res >> 15) & 1; + SREG(); + } break; + default: _avr_invalid_opcode(avr); + } + } + } break; + } + } break; + } + } break; + + case 0xb000: { + switch (opcode & 0xf800) { + case 0xb800: { // OUT A,Rr 1011 1AAr rrrr AAAA + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32; + STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]); + // todo: store to IO register + _avr_set_ram(avr, A, avr->data[r]); + // avr->data[A] = ; + } break; + case 0xb000: { // IN Rd,A 1011 0AAr rrrr AAAA + uint8_t r = (opcode >> 4) & 0x1f; + uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32; + STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]); + // todo: get the IO register + _avr_set_r(avr, r, _avr_get_ram(avr, A)); + } break; + default: _avr_invalid_opcode(avr); + } + } break; + + case 0xc000: { + // RJMP 1100 kkkk kkkk kkkk + short o = ((short)(opcode << 4)) >> 4; + STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1)); + new_pc = new_pc + (o << 1); + TRACE_JUMP(); + } break; + + case 0xd000: { + // RCALL 1100 kkkk kkkk kkkk + short o = ((short)(opcode << 4)) >> 4; + STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1)); + _avr_push16(avr, new_pc >> 1); + new_pc = new_pc + (o << 1); + TRACE_JUMP(); + } break; + + case 0xe000: { // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff) + uint8_t d = 16 + ((opcode >> 4) & 0xf); + uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf); + STATE("ldi %s, 0x%02x\n", avr_regname(d), k); + _avr_set_r(avr, d, k); + } break; + + case 0xf000: { + switch (opcode & 0xfe00) { + case 0xf000: + case 0xf200: + case 0xf400: + case 0xf600: { // All the SREG branches + short o = ((short)(opcode << 6)) >> 9; // offset + uint8_t s = opcode & 7; + int set = (opcode & 0x0400) == 0; // this bit means BRXC otherwise BRXS + int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set); + const char *names[2][8] = { + { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"}, + { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"}, + }; + if (names[set][s]) { + STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not"); + } else { + STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not"); + } + if (branch) + new_pc = new_pc + (o << 1); + } break; + case 0xf800: + case 0xf900: { // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb + uint8_t r = (opcode >> 4) & 0x1f; // register index + uint8_t s = opcode & 7; + uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0); + STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v); + _avr_set_r(avr, r, v); + } break; + case 0xfa00: + case 0xfb00:{ // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb + uint8_t r = (opcode >> 4) & 0x1f; // register index + uint8_t s = opcode & 7; + STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s); + avr->sreg[S_T] = (avr->data[r] >> s) & 1; + SREG(); + } break; + case 0xfc00: + case 0xfe00: { // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb + uint8_t r = (opcode >> 4) & 0x1f; // register index + uint8_t s = opcode & 7; + int set = (opcode & 0x0200) != 0; + int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set); + STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not"); + if (branch) + new_pc = new_pc + 2; + } break; + default: _avr_invalid_opcode(avr); + } + } break; + + default: _avr_invalid_opcode(avr); + + } + avr->cycle += cycle; + return new_pc; +} + + diff --git a/simavr/sim/sim_core.h b/simavr/sim/sim_core.h new file mode 100644 index 0000000..0fc5dd5 --- /dev/null +++ b/simavr/sim/sim_core.h @@ -0,0 +1,70 @@ +/* + sim_core.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef SIM_CORE_H_ +#define SIM_CORE_H_ + +/* + * Instruction decoder, run ONE instruction + */ +uint16_t avr_run_one(avr_t * avr); + +/* + * These are for internal access to the stack (for interupts) + */ +uint16_t _avr_sp_get(avr_t * avr); +void _avr_sp_set(avr_t * avr, uint16_t sp); +void _avr_push16(avr_t * avr, uint16_t v); + +/* + * Get a "pretty" register name + */ +const char * avr_regname(uint8_t reg); + + +/* + * DEBUG bits follow + * These will diseapear when gdb arrives + */ +void avr_dump_state(avr_t * avr); + +#define DUMP_REG() { \ + for (int i = 0; i < 32; i++) printf("%s=%02x%c", avr_regname(i), avr->data[i],i==15?'\n':' ');\ + printf("\n");\ + uint16_t y = avr->data[R_YL] | (avr->data[R_YH]<<8);\ + for (int i = 0; i < 20; i++) printf("Y+%02d=%02x ", i, avr->data[y+i]);\ + printf("\n");\ + } + + +#define CRASH() {\ + DUMP_REG();\ + printf("*** CYCLE %lld\n", avr->cycle);\ + for (int i = OLD_PC_SIZE-1; i > 0; i--) {\ + int pci = (avr->old_pci + i) & 0xf;\ + printf("\e[31m*** %04x: %-25s RESET -%d; sp %04x\e[0m\n",\ + avr->old[pci].pc, avr->codeline[avr->old[pci].pc>>1]->symbol, OLD_PC_SIZE-i, avr->old[pci].sp);\ + }\ + printf("Stack Ptr %04x/%04x = %d \n", _avr_sp_get(avr), avr->ramend, avr->ramend - _avr_sp_get(avr));\ + exit(1);\ + } + +#endif /* SIM_CORE_H_ */ diff --git a/simavr/sim/sim_elf.c b/simavr/sim/sim_elf.c new file mode 100644 index 0000000..29552a9 --- /dev/null +++ b/simavr/sim/sim_elf.c @@ -0,0 +1,174 @@ +/* + sim_elf.c + + Loads a .elf file, extract the code, the data, the eeprom and + the "mcu" specification section, also load usable code symbols + to be able to print meaningful trace information. + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sim_elf.h" + +int elf_read_firmware(const char * file, elf_firmware_t * firmware) +{ + Elf32_Ehdr elf_header; /* ELF header */ + Elf *elf = NULL; /* Our Elf pointer for libelf */ + int fd; // File Descriptor + + if ((fd = open(file, O_RDONLY)) == -1 || + (read(fd, &elf_header, sizeof(elf_header))) < sizeof(elf_header)) { + printf("could not read %s\n", file); + perror(file); + close(fd); + return -1; + } + + Elf_Data *data_data = NULL, + *data_text = NULL, + *data_ee = NULL; /* Data Descriptor */ + + memset(firmware, 0, sizeof(*firmware)); +#if ELF_SYMBOLS + //int bitesize = ((avr->flashend+1) >> 1) * sizeof(avr_symbol_t); + firmware->codesize = 32768; + int bitesize = firmware->codesize * sizeof(avr_symbol_t); + firmware->codeline = malloc(bitesize); + memset(firmware->codeline,0, bitesize); +#endif + + /* this is actualy mandatory !! otherwise elf_begin() fails */ + if (elf_version(EV_CURRENT) == EV_NONE) { + /* library out of date - recover from error */ + } + // Iterate through section headers again this time well stop when we find symbols + elf = elf_begin(fd, ELF_C_READ, NULL); + //printf("Loading elf %s : %p\n", file, elf); + + Elf_Scn *scn = NULL; /* Section Descriptor */ + + while ((scn = elf_nextscn(elf, scn)) != NULL) { + GElf_Shdr shdr; /* Section Header */ + gelf_getshdr(scn, &shdr); + char * name = elf_strptr(elf, elf_header.e_shstrndx, shdr.sh_name); + // printf("Walking elf section '%s'\n", name); + + if (!strcmp(name, ".text")) + data_text = elf_getdata(scn, NULL); + else if (!strcmp(name, ".data")) + data_data = elf_getdata(scn, NULL); + else if (!strcmp(name, ".eeprom")) + data_ee = elf_getdata(scn, NULL); + else if (!strcmp(name, ".bss")) { + Elf_Data *s = elf_getdata(scn, NULL); + firmware->bsssize = s->d_size; + } else if (!strcmp(name, ".mmcu")) { + Elf_Data *s = elf_getdata(scn, NULL); + long f_cpu = s ? *((long*)s->d_buf) : 0; + firmware->mmcu = *((avr_mcu_t*)s->d_buf); + printf("%s: setting speed to %ld\n", __FUNCTION__, f_cpu); + // avr->frequency = f_cpu; + } +#if ELF_SYMBOLS + // When we find a section header marked SHT_SYMTAB stop and get symbols + if (shdr.sh_type == SHT_SYMTAB) { + // edata points to our symbol table + Elf_Data *edata = elf_getdata(scn, NULL); + + // how many symbols are there? this number comes from the size of + // the section divided by the entry size + int symbol_count = shdr.sh_size / shdr.sh_entsize; + + // loop through to grab all symbols + for (int i = 0; i < symbol_count; i++) { + GElf_Sym sym; /* Symbol */ + // libelf grabs the symbol data using gelf_getsym() + gelf_getsym(edata, i, &sym); + + // print out the value and size + // printf("%08x %08d ", sym.st_value, sym.st_size); + if (ELF32_ST_BIND(sym.st_info) == STB_GLOBAL || + ELF32_ST_TYPE(sym.st_info) == STT_FUNC || + ELF32_ST_TYPE(sym.st_info) == STT_OBJECT) { + const char * name = elf_strptr(elf, shdr.sh_link, sym.st_name); + + // type of symbol + if (sym.st_value & 0xfff00000) { + + } else { + // code + if (firmware->codeline[sym.st_value >> 1] == NULL) { + avr_symbol_t * s = firmware->codeline[sym.st_value >> 1] = malloc(sizeof(avr_symbol_t*)); + s->symbol = strdup(name); + s->addr = sym.st_value; + } + } + } + } + } +#endif + } +#if ELF_SYMBOLS + avr_symbol_t * last = NULL; + for (int i = 0; i < firmware->codesize; i++) { + if (!firmware->codeline[i]) + firmware->codeline[i] = last; + else + last = firmware->codeline[i]; + } +#endif + uint32_t offset = 0; + firmware->flashsize = + (data_text ? data_text->d_size : 0) + + (data_data ? data_data->d_size : 0); + firmware->flash = malloc(firmware->flashsize); + if (data_text) { + // hdump("code", data_text->d_buf, data_text->d_size); + memcpy(firmware->flash + offset, data_text->d_buf, data_text->d_size); + offset += data_text->d_size; + printf("Loaded %d .text\n", data_text->d_size); + } + if (data_data) { + // hdump("data", data_data->d_buf, data_data->d_size); + memcpy(firmware->flash + offset, data_data->d_buf, data_data->d_size); + printf("Loaded %d .data\n", data_data->d_size); + offset += data_data->d_size; + firmware->datasize = data_data->d_size; + } + if (data_ee) { + // hdump("eeprom", data_ee->d_buf, data_ee->d_size); + firmware->eeprom = malloc(data_ee->d_size); + memcpy(firmware->eeprom, data_ee->d_buf, data_ee->d_size); + printf("Loaded %d .eeprom\n", data_ee->d_size); + firmware->eesize = data_ee->d_size; + } +// hdump("flash", avr->flash, offset); + elf_end(elf); + close(fd); + return 0; +} + diff --git a/simavr/sim/sim_elf.h b/simavr/sim/sim_elf.h new file mode 100644 index 0000000..05af0a7 --- /dev/null +++ b/simavr/sim/sim_elf.h @@ -0,0 +1,53 @@ +/* + sim_elf.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef ELF_H_ +#define ELF_H_ + +#include "avr_mcu_section.h" + +#ifndef ELF_SYMBOLS +#define ELF_SYMBOLS 1 +#endif + +#if ELF_SYMBOLS +#include "simavr.h" +#endif + +typedef struct elf_firmware_t { + avr_mcu_t mmcu; + uint8_t * flash; + uint32_t flashsize; + uint32_t datasize; + uint32_t bsssize; + // read the .eeprom section of the elf, too + uint8_t * eeprom; + uint32_t eesize; + +#if ELF_SYMBOLS + avr_symbol_t ** codeline; + uint32_t codesize; // in elements +#endif +} elf_firmware_t ; + +int elf_read_firmware(const char * file, elf_firmware_t * firmware); + +#endif /* ELF_H_ */ diff --git a/simavr/sim/sim_gdb.c b/simavr/sim/sim_gdb.c new file mode 100644 index 0000000..74714d1 --- /dev/null +++ b/simavr/sim/sim_gdb.c @@ -0,0 +1,66 @@ +/* + sim_gdb.c + + Placeholder! + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "simavr.h" + +typedef struct avr_gdb_t { + avr_t * avr; + int sock; +} avr_gdb_t; + +int avr_gdb_init(avr_t * avr) +{ + avr_gdb_t * g = malloc(sizeof(avr_gdb_t)); + memset(g, 0, sizeof(avr_gdb_t)); + + avr->gdb = NULL; + + if ((g->sock = socket(PF_INET, SOCK_STREAM, 0)) < 0) { + fprintf(stderr, "Can't create socket: %s", strerror(errno)); + return -1; + } + + int i = 1; + setsockopt(g->sock, SOL_SOCKET, SO_REUSEADDR, &i, sizeof(i)); + + struct sockaddr_in address = { 0 }; + address.sin_family = AF_INET; + address.sin_port = htons (1234); + + if (bind(g->sock, (struct sockaddr *) &address, sizeof(address))) { + fprintf(stderr, "Can not bind socket: %s", strerror(errno)); + return -1; + } + avr->gdb = g; + return 0; +} diff --git a/simavr/sim/sim_gdb.h b/simavr/sim/sim_gdb.h new file mode 100644 index 0000000..67f7a07 --- /dev/null +++ b/simavr/sim/sim_gdb.h @@ -0,0 +1,25 @@ +/* + sim_gdb.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __SIM_GDB_H__ +#define __SIM_GDB_H__ + +#endif diff --git a/simavr/sim/simavr.c b/simavr/sim/simavr.c new file mode 100644 index 0000000..39481dc --- /dev/null +++ b/simavr/sim/simavr.c @@ -0,0 +1,356 @@ +/* + simavr.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include "simavr.h" +#include "sim_elf.h" + +#include "sim_core.h" +#include "avr_eeprom.h" + +void hdump(const char *w, uint8_t *b, size_t l) +{ + uint32_t i; + if (l < 16) { + printf("%s: ",w); + for (i = 0; i < l; i++) printf("%02x",b[i]); + } else { + printf("%s:\n",w); + for (i = 0; i < l; i++) { + if (!(i & 0x1f)) printf(" "); + printf("%02x",b[i]); + if ((i & 0x1f) == 0x1f) { + printf(" "); + printf("\n"); + } + } + } + printf("\n"); +} + + + +int avr_init(avr_t * avr) +{ + avr->flash = malloc(avr->flashend + 1); + memset(avr->flash, 0xff, avr->flashend + 1); + avr->data = malloc(avr->ramend + 1); + memset(avr->data, 0, avr->ramend + 1); + + avr->state = cpu_Running; + avr->frequency = 1000000; // can be overriden via avr_mcu_section + + if (avr->init) + avr->init(avr); + avr_reset(avr); + return 0; +} + +void avr_reset(avr_t * avr) +{ + memset(avr->data, 0x0, avr->ramend + 1); + _avr_sp_set(avr, avr->ramend); + avr->pc = 0; + for (int i = 0; i < 8; i++) + avr->sreg[i] = 0; + if (avr->reset) + avr->reset(avr); + + avr_io_t * port = avr->io_port; + while (port) { + if (port->reset) + port->reset(avr, port); + port = port->next; + } + +} + +int avr_ioctl(avr_t *avr, uint32_t ctl, void * io_param) +{ + avr_io_t * port = avr->io_port; + int res = -1; + while (port && res == -1) { + if (port->ioctl) + res = port->ioctl(avr, port, ctl, io_param); + port = port->next; + } + return res; +} + +void avr_register_io(avr_t *avr, avr_io_t * io) +{ + io->next = avr->io_port; + avr->io_port = io; +} + +void avr_register_io_read(avr_t *avr, uint8_t addr, avr_io_read_t readp, void * param) +{ + avr->ior[AVR_DATA_TO_IO(addr)].param = param; + avr->ior[AVR_DATA_TO_IO(addr)].r = readp; +} + +void avr_register_io_write(avr_t *avr, uint8_t addr, avr_io_write_t writep, void * param) +{ + avr->iow[AVR_DATA_TO_IO(addr)].param = param; + avr->iow[AVR_DATA_TO_IO(addr)].w = writep; +} + +void avr_register_vector(avr_t *avr, avr_int_vector_t * vector) +{ + if (vector->vector) + avr->vector[vector->vector] = vector; +} + +int avr_has_pending_interupts(avr_t * avr) +{ + return avr->pending[0] || avr->pending[1]; +} + +int avr_is_interupt_pending(avr_t * avr, avr_int_vector_t * vector) +{ + return avr->pending[vector->vector >> 5] & (1 << (vector->vector & 0x1f)); +} + +void avr_raise_interupt(avr_t * avr, avr_int_vector_t * vector) +{ + if (!vector->vector) + return; +// printf("%s raising %d\n", __FUNCTION__, vector->vector); + if (vector->enable.reg) { + if (!avr_regbit_get(avr, vector->enable)) + return; + } + if (!avr_is_interupt_pending(avr, vector)) { + if (!avr->pending_wait) + avr->pending_wait = 2; // latency on interupts ?? + avr->pending[vector->vector >> 5] |= (1 << (vector->vector & 0x1f)); + + if (vector->raised.reg) + avr_regbit_set(avr, vector->raised); + if (avr->state != cpu_Running) { + // printf("Waking CPU due to interrupt\n"); + avr->state = cpu_Running; // in case we were sleeping + } + } +} + +static void avr_clear_interupt(avr_t * avr, int v) +{ + avr_int_vector_t * vector = avr->vector[v]; + avr->pending[v >> 5] &= ~(1 << (v & 0x1f)); + if (!vector) + return; + printf("%s cleared %d\n", __FUNCTION__, vector->vector); + if (vector->raised.reg) + avr_regbit_clear(avr, vector->raised); +} + +void avr_loadcode(avr_t * avr, uint8_t * code, uint32_t size, uint32_t address) +{ + memcpy(avr->flash + address, code, size); +} + +void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v) +{ + if (addr > avr->ramend) { + printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n", + avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v); + CRASH(); + } + if (addr < 32) { + printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n", + avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v); + CRASH(); + } +#if 0 + /* + * this only happend when the compiler is doctoring the stack before calls. Or + * if there is an invalid pointer somewhere... + */ + if (addr > _avr_sp_get(avr)) { + avr->trace++; + STATE("\e[31mmunching stack SP %04x, A=%04x <= %02x\e[0m\n", _avr_sp_get(avr), addr, v); + avr->trace--; + } +#endif + avr->data[addr] = v; +} + +uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr) +{ + if (addr > avr->ramend) { + printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n", + avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend); + CRASH(); + } + return avr->data[addr]; +} + +/* + * check wether interupts are pending. I so, check if the interupt "latency" is reached, + * and if so triggers the handlers and jump to the vector. + */ +static void avr_service_interupts(avr_t * avr) +{ + if (!avr->sreg[S_I]) + return; + + if (avr_has_pending_interupts(avr)) { + if (avr->pending_wait) { + avr->pending_wait--; + if (avr->pending_wait == 0) { + int done = 0; + for (int bi = 0; bi < 2 && !done; bi++) if (avr->pending[bi]) { + for (int ii = 0; ii < 32 && !done; ii++) + if (avr->pending[bi] & (1 << ii)) { + + int v = (bi * 32) + ii; // vector + + // printf("%s calling %d\n", __FUNCTION__, v); + _avr_push16(avr, avr->pc >> 1); + avr->sreg[S_I] = 0; + avr->pc = v * avr->vector_size; + + avr_clear_interupt(avr, v); + done++; + break; + } + break; + } + } + } else + avr->pending_wait = 2; // for next one... + } +} + + +int avr_run(avr_t * avr) +{ + if (avr->state == cpu_Stopped) + return avr->state; + + uint16_t new_pc = avr->pc; + + if (avr->state == cpu_Running) { + new_pc = avr_run_one(avr); + avr_dump_state(avr); + } else + avr->cycle ++; + + // re-synth the SREG + //SREG(); + // if we just re-enabled the interrupts... + if (avr->sreg[S_I] && !(avr->data[R_SREG] & (1 << S_I))) { + // printf("*** %s: Renabling interupts\n", __FUNCTION__); + avr->pending_wait++; + } + avr_io_t * port = avr->io_port; + while (port) { + if (port->run) + port->run(avr, port); + port = port->next; + } + + avr->pc = new_pc; + + if (avr->state == cpu_Sleeping) { + if (!avr->sreg[S_I]) { + printf("simavr: sleeping with interupts off, quitting gracefuly\n"); + exit(0); + } + usleep(500); + long sleep = (float)avr->frequency * (1.0f / 500.0f); + avr->cycle += sleep; + // avr->state = cpu_Running; + } + // Interrupt servicing might change the PC too + if (avr->state == cpu_Running || avr->state == cpu_Sleeping) { + avr_service_interupts(avr); + + avr->data[R_SREG] = 0; + for (int i = 0; i < 8; i++) + if (avr->sreg[i] > 1) { + printf("** Invalid SREG!!\n"); + CRASH(); + } else if (avr->sreg[i]) + avr->data[R_SREG] |= (1 << i); + } + return avr->state; +} + +extern avr_kind_t tiny85; +extern avr_kind_t mega48,mega88,mega168; +extern avr_kind_t mega644; + +avr_kind_t * avr_kind[] = { + &tiny85, + &mega48, + &mega88, + &mega168, + &mega644, + NULL +}; + +int main(int argc, const char **argv) +{ + elf_firmware_t f; + + elf_read_firmware(argv[1], &f); + + printf("firmware %s f=%ld mmcu=%s\n", argv[1], f.mmcu.f_cpu, f.mmcu.name); + + avr_kind_t * maker = NULL; + for (int i = 0; avr_kind[i] && !maker; i++) { + for (int j = 0; avr_kind[i]->names[j]; j++) + if (!strcmp(avr_kind[i]->names[j], f.mmcu.name)) { + maker = avr_kind[i]; + break; + } + } + if (!maker) { + fprintf(stderr, "%s: AVR '%s' now known\n", argv[0], f.mmcu.name); + exit(1); + } + + avr_t * avr = maker->make(); + printf("Starting %s - flashend %04x ramend %04x e2end %04x\n", avr->mmcu, avr->flashend, avr->ramend, avr->e2end); + avr_init(avr); + avr->frequency = f.mmcu.f_cpu; + avr->codeline = f.codeline; + avr_loadcode(avr, f.flash, f.flashsize, 0); + avr->codeend = f.flashsize - f.datasize; + if (f.eeprom && f.eesize) { + avr_eeprom_desc_t d = { .ee = f.eeprom, .offset = 0, .size = f.eesize }; + avr_ioctl(avr, AVR_IOCTL_EEPROM_SET, &d); + } +// avr->trace = 1; + + for (long long i = 0; i < 8000000*10; i++) +// for (long long i = 0; i < 80000; i++) + avr_run(avr); + +} diff --git a/simavr/sim/simavr.h b/simavr/sim/simavr.h new file mode 100644 index 0000000..bc1fd3f --- /dev/null +++ b/simavr/sim/simavr.h @@ -0,0 +1,313 @@ +/* + simavr.h + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __SIMAVR_H__ +#define __SIMAVR_H__ + +#include + +struct avr_t; +typedef uint8_t (*avr_io_read_t)(struct avr_t * avr, uint8_t addr, void * param); +typedef void (*avr_io_write_t)(struct avr_t * avr, uint8_t addr, uint8_t v, void * param); + +enum { + // SREG bit indexes + S_C = 0,S_Z,S_N,S_V,S_S,S_H,S_T,S_I, + + // 16 bits register pairs + R_XL = 0x1a, R_XH,R_YL,R_YH,R_ZL,R_ZH, + // stack pointer + R_SPL = 32+0x3d, R_SPH, + // real SREG + R_SREG = 32+0x3f, + + // maximum number of IO regisrer, on normal AVRs + MAX_IOs = 256 - 32, // minus 32 GP registers +}; + +#define AVR_DATA_TO_IO(v) ((v) - 32) +#define AVR_IO_TO_DATA(v) ((v) + 32) + +/* + * Core states. This will need populating with debug states for gdb + */ +enum { + cpu_Stopped, + cpu_Running, + cpu_Sleeping, +}; + +/* + * Main AVR instance. Some of these fields are set by the AVR "Core" definition files + * the rest is runtime data (as little as possible) + */ +typedef struct avr_t { + const char * mmcu; // name of the AVR + // these are filled by sim_core_declare from constants in /usr/lib/avr/include/avr/io*.h + uint16_t ramend; + uint32_t flashend; + uint32_t e2end; + uint8_t vector_size; + uint8_t signature[3]; + uint8_t fuse[4]; + + // filled by the ELF data, this allow tracking of invalid jumps + uint32_t codeend; + + int state; // stopped, running, sleeping + uint32_t frequency; // frequency we are running at + uint64_t cycle; // current cycle + + // called at init time + void (*init)(struct avr_t * avr); + // called at reset time + void (*reset)(struct avr_t * avr); + + // Mirror of the SREG register, to facilitate the access to bits + // in the opcode decoder. + // This array is re-synthetized back/forth when SREG changes + uint8_t sreg[8]; + + /* + * ** current PC ** + * Note that the PC is reoresenting /bytes/ while the AVR value is + * assumed to be "words". This is in line with what GDB does... + * this is why you will see >>1 ane <<1 in the decoder to handle jumps + */ + uint32_t pc; + + /* + * callback when specific IO registers are read/written + */ + struct { + void * param; + avr_io_read_t r; + } ior[MAX_IOs]; + struct { + void * param; + avr_io_write_t w; + } iow[MAX_IOs]; + + // flash memory (initialized to 0xff, and code loaded into it) + uint8_t * flash; + // this is the general purpose registers, IO registers, and SRAM + uint8_t * data; + + // queue of io modules + struct avr_io_t *io_port; + + // interupt vectors, and their enable/clear registers + struct avr_int_vector_t * vector[64]; + uint8_t pending_wait; // number of cycles to wait for pending + uint32_t pending[2]; // pending interupts + + // DEBUG ONLY + int trace; + struct avr_symbol_t ** codeline; + + /* DEBUG ONLY + * this keeps track of "jumps" ie, call,jmp,ret,reti and so on + * allows dumping of a meaningful data even if the stack is + * munched and so on + */ + #define OLD_PC_SIZE 32 + struct { + uint32_t pc; + uint16_t sp; + } old[OLD_PC_SIZE]; // catches reset.. + int old_pci; + + // DEBUG ONLY + // keeps track of wich registers gets touched by instructions + // reset before each new instructions. Allows meaningful traces + uint32_t touched[256 / 32]; // debug + + // placeholder + struct avr_gdb_t * gdb; +} avr_t; + + +// this is a static constructor for each of the AVR devices +typedef struct avr_kind_t { + const char * names[4]; // name aliases + avr_t * (*make)(); +} avr_kind_t; + +// a symbol loaded from the .elf file +typedef struct avr_symbol_t { + const char * symbol; + uint32_t addr; +} avr_symbol_t; + +/* + * this 'structure' is a packed representation of an IO register 'bit' + * (or consecutive bits). This allows a way to set/get/clear them. + * gcc is happy passing these as register value, so you don't need to + * use a pointer when passing them along to functions. + */ +typedef struct avr_regbit_t { + unsigned long reg : 8, bit : 3, mask : 8; +} avr_regbit_t; + +// interupt vector for the IO modules +typedef struct avr_int_vector_t { + uint8_t vector; // vector number, zero (reset) is reserved + + avr_regbit_t enable; // IO register index for the "interupt enable" flag for this vector + avr_regbit_t raised; // IO register index for the register where the "raised" flag is (optional) +} avr_int_vector_t; + +/* + * used by the ioports to implement their own features + * see avr_eeprom.* for an example, and avr_ioctl(). + */ +#define AVR_IOCTL_DEF(_a,_b,_c,_d) \ + (((_a) << 24)|((_b) << 16)|((_c) << 8)|((_d))) + +/* + * IO module base struct + * Modules uses that as their first member in their own struct + */ +typedef struct avr_io_t { + struct avr_io_t * next; + const char * kind; + // called at every instruction + void (*run)(avr_t * avr, struct avr_io_t *io); + // called at reset time + void (*reset)(avr_t * avr, struct avr_io_t *io); + // called externally. allow access to io modules and so on + int (*ioctl)(avr_t * avr, struct avr_io_t *io, uint32_t ctl, void *io_param); +} avr_io_t; + +// initializes a new AVR instance. Will call the IO registers init(), and then reset() +int avr_init(avr_t * avr); +// resets the AVR, and the IO modules +void avr_reset(avr_t * avr); + +// load code in the "flash" +void avr_loadcode(avr_t * avr, uint8_t * code, uint32_t size, uint32_t address); + +/* + * IO modules helper functions + */ + +// registers an IO module, so it's run(), reset() etc are called +// this is called by the AVR core init functions, you /could/ register an external +// one after instanciation, for whatever purpose... +void avr_register_io(avr_t *avr, avr_io_t * io); +// register a callback for when IO register "addr" is read +void avr_register_io_read(avr_t *avr, uint8_t addr, avr_io_read_t read, void * param); +// register a callback for when the IO register is written. callback has to set the memory itself +void avr_register_io_write(avr_t *avr, uint8_t addr, avr_io_write_t write, void * param); +// call every IO modules until one responds to this +int avr_ioctl(avr_t *avr, uint32_t ctl, void * io_param); + +/* + * Interupt Helper Functions + */ +// register an interupt vector. It's only needed if you want to use the "r_raised" flags +void avr_register_vector(avr_t *avr, avr_int_vector_t * vector); +// raise an interupt (if enabled). The interupt is latched and will be called later +void avr_raise_interupt(avr_t * avr, avr_int_vector_t * vector); +// return non-zero if the AVR core has any pending interupts +int avr_has_pending_interupts(avr_t * avr); +// return nonzero if a soecific interupt vector is pending +int avr_is_interupt_pending(avr_t * avr, avr_int_vector_t * vector); + +/* + * these are accessors for avr->data but allows watchpoints to be set for gdb + * IO modules use that to set values to registers, and the AVR core decoder uses + * that to register "public" read by instructions. + */ +void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v); +uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr); + + +/* + * These accessors are inlined and are used to perform the operations on + * avr_regbit_t definitions. This is the "official" way to access bits into registers + * The small footorint costs brings much better versatility for functions/bits that are + * not always defined in the same place on real AVR cores + */ +/* + * set/get/clear io register bits in one operation + */ +static inline uint8_t avr_regbit_set(avr_t * avr, avr_regbit_t rb) +{ + uint8_t a = rb.reg; + if (!a) + return 0; + uint8_t m = rb.mask << rb.bit; + avr_core_watch_write(avr, a, avr->data[a] | m); + return (avr->data[a] >> rb.bit) & rb.mask; +} + +static inline uint8_t avr_regbit_setto(avr_t * avr, avr_regbit_t rb, uint8_t v) +{ + uint8_t a = rb.reg; + if (!a) + return 0; + uint8_t m = rb.mask << rb.bit; + avr_core_watch_write(avr, a, (avr->data[a] & ~(m)) | ((v << rb.bit) & m)); + return (avr->data[a] >> rb.bit) & rb.mask; +} + +static inline uint8_t avr_regbit_get(avr_t * avr, avr_regbit_t rb) +{ + uint8_t a = rb.reg; + if (!a) + return 0; + //uint8_t m = rb.mask << rb.bit; + return (avr->data[a] >> rb.bit) & rb.mask; +} + +static inline uint8_t avr_regbit_clear(avr_t * avr, avr_regbit_t rb) +{ + uint8_t a = (rb.reg); + uint8_t m = rb.mask << rb.bit; + avr_core_watch_write(avr, a, avr->data[a] & ~m); + return avr->data[a]; +} + +#define ARRAY_SIZE(_aa) (sizeof(_aa) / sizeof((_aa)[0])) + +/* + * This reads the bits for an array of avr_regbit_t, make up a "byte" with them. + * This allows reading bits like CS0, CS1, CS2 etc even if they are not in the same + * physical IO register. + */ +static inline uint8_t avr_regbit_get_array(avr_t * avr, avr_regbit_t *rb, int count) +{ + uint8_t res = 0; + + for (int i = 0; i < count; i++, rb++) if (rb->reg) { + uint8_t a = (rb->reg); + res |= ((avr->data[a] >> rb->bit) & rb->mask) << i; + } + return res; +} + +#define AVR_IO_REGBIT(_io, _bit) { . reg = (_io), .bit = (_bit), .mask = 1 } +#define AVR_IO_REGBITS(_io, _bit, _mask) { . reg = (_io), .bit = (_bit), .mask = (_mask) } + + +#endif /*__SIMAVR_H__*/ + diff --git a/tests/Makefile b/tests/Makefile new file mode 100644 index 0000000..ff2ede5 --- /dev/null +++ b/tests/Makefile @@ -0,0 +1,54 @@ +# +# This makefile take each "at*" file, extracts it's part name +# And compile it into an ELF binary. +# It also disassemble it for debugging purposes. +# +# The code is compiled "optimized" to the max. +# +# The wierd "-Wl,--undefined=_mmcu,--section-start=.mmcu=0x910000" +# is used to tell the linker not to discard the .mmcu section, +# otherwise the --gc-sections will delete it. +# +# Copyright 2008, 2009 Michel Pollet +# +# This file is part of simavr. +# +# simavr is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# simavr is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with simavr. If not, see . + +sources := $(wildcard at*.c) + +all : ${sources:.c=.axf} ${sources:.c=.hex} ${sources:.c=.s} + +%.hex: %.axf + @avr-objcopy -j .text -j .data -O ihex ${<} ${@} + +%.s: %.axf + @avr-objdump -j .text -j .data -j .bss -d ${<} > ${@} + +%.axf: %.c + @echo CC ${<} + @part=${<} ; part=$${part/_*}; \ + avr-gcc -Wall -g -Os -std=gnu99 \ + -mmcu=$$part \ + -DF_CPU=8000000 \ + -mcall-prologues -fno-inline-small-functions \ + -ffunction-sections -fdata-sections \ + -Wl,--relax,--gc-sections \ + -Wl,--undefined=_mmcu,--section-start=.mmcu=0x910000 \ + -I../include \ + ${<} -o ${@} + @avr-size ${@}|sed '1d' + +clean: + rm -f *.hex *.o *.axf *.s diff --git a/tests/atmega88_example.c b/tests/atmega88_example.c new file mode 100644 index 0000000..fd15e94 --- /dev/null +++ b/tests/atmega88_example.c @@ -0,0 +1,54 @@ +/* + atmega88_example.c + + */ + +#ifndef F_CPU +#define F_CPU 8000000 +#endif +#include +#include +#include +#include +#include + +/* + * This demonstrate how to use the avr_mcu_section.h file + * The macro adds a section to the ELF file with useful + * information for the simulator + */ +#include "avr_mcu_section.h" +AVR_MCU(F_CPU, "atmega88"); + +/* declare this in a .eeprom ELF section */ +uint32_t value EEMEM = 0xdeadbeef; + +static int uart_putchar(char c, FILE *stream) { + if (c == '\n') + uart_putchar('\r', stream); + loop_until_bit_is_set(UCSR0A, UDRE0); + UDR0 = c; + return 0; +} + +static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, + _FDEV_SETUP_WRITE); + + +int main() +{ + stdout = &mystdout; + + // read the eeprom value + uint32_t c = eeprom_read_dword((void*)&value); + printf("Read from eeprom 0x%08lx -- should be 0xdeadbeef\n", c); + // change the eeprom + eeprom_write_dword((void*)&value, 0xcafef00d); + // re-read it + c = eeprom_read_dword((void*)&value); + printf("Read from eeprom 0x%08lx -- should be 0xcafef00d\n", c); + + // this quits the simulator, since interupts are off + // this is a "feature" that allows running tests cases and exit + sleep_cpu(); +}