From d5d8c51763b7da7b17f8f7ed1459174865d29944 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Tue, 13 Sep 2011 19:38:38 +0100 Subject: [PATCH] cores: Added mega8, old generation Possibly would work with mega16, 32 ? Signed-off-by: Michel Pollet --- simavr/cores/sim_mega8.c | 43 ++++++ simavr/cores/sim_megax.c | 53 +++++++ simavr/cores/sim_megax.h | 325 +++++++++++++++++++++++++++++++++++++++ simavr/sim/sim_avr.c | 10 +- 4 files changed, 429 insertions(+), 2 deletions(-) create mode 100644 simavr/cores/sim_mega8.c create mode 100644 simavr/cores/sim_megax.c create mode 100644 simavr/cores/sim_megax.h diff --git a/simavr/cores/sim_mega8.c b/simavr/cores/sim_mega8.c new file mode 100644 index 0000000..7bd2934 --- /dev/null +++ b/simavr/cores/sim_mega8.c @@ -0,0 +1,43 @@ +/* + sim_mega88.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "sim_avr.h" + +#define SIM_VECTOR_SIZE 2 +#define SIM_MMCU "atmega8" +#define SIM_CORENAME mcu_mega8 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom8.h" +// instanciate the new core +#include "sim_megax.h" + +static avr_t * make() +{ + return &SIM_CORENAME.core; +} + +avr_kind_t mega8 = { + .names = { "atmega8", "atmega8l" }, + .make = make +}; + diff --git a/simavr/cores/sim_megax.c b/simavr/cores/sim_megax.c new file mode 100644 index 0000000..a9e3ca5 --- /dev/null +++ b/simavr/cores/sim_megax.c @@ -0,0 +1,53 @@ +/* + sim_megax.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include +#include "sim_avr.h" + + +#include "sim_megax.h" + +void mx_init(struct avr_t * avr) +{ + struct mcu_t * mcu = (struct mcu_t*)avr; + + printf("%s init\n", avr->mmcu); + + avr_eeprom_init(avr, &mcu->eeprom); + avr_flash_init(avr, &mcu->selfprog); + avr_watchdog_init(avr, &mcu->watchdog); + avr_extint_init(avr, &mcu->extint); + avr_ioport_init(avr, &mcu->portb); + avr_ioport_init(avr, &mcu->portc); + avr_ioport_init(avr, &mcu->portd); + avr_uart_init(avr, &mcu->uart); + avr_adc_init(avr, &mcu->adc); + avr_timer_init(avr, &mcu->timer0); + avr_timer_init(avr, &mcu->timer1); + avr_timer_init(avr, &mcu->timer2); + avr_spi_init(avr, &mcu->spi); + avr_twi_init(avr, &mcu->twi); +} + +void mx_reset(struct avr_t * avr) +{ +// struct mcu_t * mcu = (struct mcu_t*)avr; +} diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h new file mode 100644 index 0000000..e266132 --- /dev/null +++ b/simavr/cores/sim_megax.h @@ -0,0 +1,325 @@ +/* + sim_mega128.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#ifndef __SIM_MEGAX_H__ +#define __SIM_MEGAX_H__ + +#include "sim_core_declare.h" +#include "avr_eeprom.h" +#include "avr_flash.h" +#include "avr_watchdog.h" +#include "avr_extint.h" +#include "avr_ioport.h" +#include "avr_uart.h" +#include "avr_adc.h" +#include "avr_timer.h" +#include "avr_spi.h" +#include "avr_twi.h" + +void mx_init(struct avr_t * avr); +void mx_reset(struct avr_t * avr); + +/* + * This is a template for all of the 8/32/64 devices, hopefuly + */ +struct mcu_t { + avr_t core; + avr_eeprom_t eeprom; + avr_flash_t selfprog; + avr_watchdog_t watchdog; + avr_extint_t extint; + avr_ioport_t portb, portc, portd; + avr_uart_t uart; + avr_adc_t adc; + avr_timer_t timer0,timer1,timer2; + avr_spi_t spi; + avr_twi_t twi; +}; + +#ifdef SIM_CORENAME + +#ifndef SIM_VECTOR_SIZE +#error SIM_VECTOR_SIZE is not declared +#endif +#ifndef SIM_MMCU +#error SIM_MMCU is not declared +#endif + +#ifndef EFUSE_DEFAULT +#define EFUSE_DEFAULT 0xff +#endif +#define EICRA MCUCR +#define EIMSK GICR +#define EIFR GIFR + +struct mcu_t SIM_CORENAME = { + .core = { + .mmcu = SIM_MMCU, + DEFAULT_CORE(SIM_VECTOR_SIZE), + + .init = mx_init, + .reset = mx_reset, + }, + AVR_EEPROM_DECLARE_NOEEPM(EE_RDY_vect), + AVR_SELFPROG_DECLARE(SPMCR, SPMEN, SPM_RDY_vect), + AVR_WATCHDOG_DECLARE_128(WDTCR, _VECTOR(0)), + .extint = { + AVR_EXTINT_DECLARE(0, 'D', PD2), + AVR_EXTINT_DECLARE(1, 'D', PD3), + }, + .portb = { + .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB, + }, + .portc = { + .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC, + }, + .portd = { + .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND, + }, + + .uart = { + // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART0), + .name = '0', + .r_udr = UDR, + + .txen = AVR_IO_REGBIT(UCSRB, TXEN), + .rxen = AVR_IO_REGBIT(UCSRB, RXEN), + .ucsz = AVR_IO_REGBITS(UCSRC, UCSZ0, 0x3), // 2 bits + .ucsz2 = AVR_IO_REGBIT(UCSRB, UCSZ2), // 1 bits + + .r_ucsra = UCSRA, + .r_ucsrb = UCSRB, + .r_ucsrc = UCSRC, + .r_ubrrl = UBRRL, + .r_ubrrh = UBRRH, + .rxc = { + .enable = AVR_IO_REGBIT(UCSRB, RXCIE), + .raised = AVR_IO_REGBIT(UCSRA, RXC), + .vector = USART_RXC_vect, + }, + .txc = { + .enable = AVR_IO_REGBIT(UCSRB, TXCIE), + .raised = AVR_IO_REGBIT(UCSRA, TXC), + .vector = USART_TXC_vect, + }, + .udrc = { + .enable = AVR_IO_REGBIT(UCSRB, UDRIE), + .raised = AVR_IO_REGBIT(UCSRA, UDRE), + .vector = USART_UDRE_vect, + }, + }, + .adc = { + .r_admux = ADMUX, + .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1), + AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),}, + .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)}, + .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256 }, + + .adlar = AVR_IO_REGBIT(ADMUX, ADLAR), + .r_adcsra = ADCSRA, + .aden = AVR_IO_REGBIT(ADCSRA, ADEN), + .adsc = AVR_IO_REGBIT(ADCSRA, ADSC), + // no ADATE .adate = AVR_IO_REGBIT(ADCSRA, ADATE), + .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),}, + + .r_adch = ADCH, + .r_adcl = ADCL, + + //.r_adcsrb = ADCSRB, + // .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),}, + + .muxmode = { + [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1), + [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3), + [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5), + [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7), + + [14] = AVR_ADC_REF(1300), // 1.30V + [15] = AVR_ADC_REF(0), // GND + }, + + .adc = { + .enable = AVR_IO_REGBIT(ADCSRA, ADIE), + .raised = AVR_IO_REGBIT(ADCSRA, ADIF), + .vector = ADC_vect, + }, + }, + .timer0 = { + .name = '0', + .cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) }, + // .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */}, + + .r_tcnt = TCNT0, + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE0), + .raised = AVR_IO_REGBIT(TIFR, TOV0), + .vector = TIMER0_OVF_vect, + }, + }, + .timer1 = { + .name = '1', + .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11), + AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) }, + .wgm_op = { + [0] = AVR_TIMER_WGM_NORMAL16(), + // TODO: 1 PWM phase correct 8bit + // 2 PWM phase correct 9bit + // 3 PWM phase correct 10bit + [4] = AVR_TIMER_WGM_CTC(), + [5] = AVR_TIMER_WGM_FASTPWM8(), + [6] = AVR_TIMER_WGM_FASTPWM9(), + [7] = AVR_TIMER_WGM_FASTPWM10(), + // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11 + [12] = AVR_TIMER_WGM_ICCTC(), + [14] = AVR_TIMER_WGM_ICPWM(), + [15] = AVR_TIMER_WGM_OCPWM(), + }, + .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */}, + + .r_tcnt = TCNT1L, + .r_icr = ICR1L, + .r_icrh = ICR1H, + .r_tcnth = TCNT1H, + + .ices = AVR_IO_REGBIT(TCCR1B, ICES1), + .icp = AVR_IO_REGBIT(PORTD, 4), + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE1), + .raised = AVR_IO_REGBIT(TIFR, TOV1), + .vector = TIMER1_OVF_vect, + }, + .icr = { + .enable = AVR_IO_REGBIT(TIMSK, TICIE1), + .raised = AVR_IO_REGBIT(TIFR, ICF1), + .vector = TIMER1_CAPT_vect, + }, + .comp = { + [AVR_TIMER_COMPA] = { + .r_ocr = OCR1AL, + .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it + .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3), + .com_pin = AVR_IO_REGBIT(PORTB, PB5), + .interrupt = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1A), + .raised = AVR_IO_REGBIT(TIFR, OCF1A), + .vector = TIMER1_COMPA_vect, + }, + }, + [AVR_TIMER_COMPB] = { + .r_ocr = OCR1BL, + .r_ocrh = OCR1BH, + .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3), + .com_pin = AVR_IO_REGBIT(PORTB, PB6), + .interrupt = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE1B), + .raised = AVR_IO_REGBIT(TIFR, OCF1B), + .vector = TIMER1_COMPB_vect, + }, + }, + }, + + }, + .timer2 = { + .name = '2', + .wgm = { AVR_IO_REGBIT(TCCR2, WGM20), AVR_IO_REGBIT(TCCR2, WGM21) }, + .wgm_op = { + [0] = AVR_TIMER_WGM_NORMAL8(), + // TODO 1 pwm phase correct + [2] = AVR_TIMER_WGM_CTC(), + [3] = AVR_TIMER_WGM_FASTPWM8(), + }, + .cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) }, + .cs_div = { 0, 0, 3 /* 8 */, 4 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ }, + + .r_tcnt = TCNT2, + + // asynchronous timer source bit.. if set, use 32khz frequency + .as2 = AVR_IO_REGBIT(ASSR, AS2), + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK, TOIE2), + .raised = AVR_IO_REGBIT(TIFR, TOV2), + .vector = TIMER2_OVF_vect, + }, + .comp = { + [AVR_TIMER_COMPA] = { + .r_ocr = OCR2, + .com = AVR_IO_REGBITS(TCCR2, COM20, 0x3), + .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C + .interrupt = { + .enable = AVR_IO_REGBIT(TIMSK, OCIE2), + .raised = AVR_IO_REGBIT(TIFR, OCF2), + .vector = TIMER2_COMP_vect, + }, + }, + }, + }, + .spi = { + + .r_spdr = SPDR, + .r_spcr = SPCR, + .r_spsr = SPSR, + + .spe = AVR_IO_REGBIT(SPCR, SPE), + .mstr = AVR_IO_REGBIT(SPCR, MSTR), + + .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) }, + .spi = { + .enable = AVR_IO_REGBIT(SPCR, SPIE), + .raised = AVR_IO_REGBIT(SPSR, SPIF), + .vector = SPI_STC_vect, + }, + }, + + .twi = { + + .r_twcr = TWCR, + .r_twsr = TWSR, + .r_twbr = TWBR, + .r_twdr = TWDR, + .r_twar = TWAR, + // no .r_twamr = TWAMR, + + .twen = AVR_IO_REGBIT(TWCR, TWEN), + .twea = AVR_IO_REGBIT(TWCR, TWEA), + .twsta = AVR_IO_REGBIT(TWCR, TWSTA), + .twsto = AVR_IO_REGBIT(TWCR, TWSTO), + .twwc = AVR_IO_REGBIT(TWCR, TWWC), + + .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits + .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits + + .twi = { + .enable = AVR_IO_REGBIT(TWCR, TWIE), + .raised = AVR_IO_REGBIT(TWCR, TWINT), + .vector = TWI_vect, + }, + }, + +}; + +#endif /* SIM_CORENAME */ + +#endif /* __SIM_MEGAX_H__ */ diff --git a/simavr/sim/sim_avr.c b/simavr/sim/sim_avr.c index 9ea353e..fc42e1f 100644 --- a/simavr/sim/sim_avr.c +++ b/simavr/sim/sim_avr.c @@ -137,15 +137,19 @@ static void _avr_io_console_write(struct avr_t * avr, avr_io_addr_t addr, uint8_ static char * buf = NULL; static int size = 0, len = 0; - if (v == '\r') { + if (v == '\r' && buf) { + buf[len] = 0; printf("O:" "%s" "" "\n", buf); fflush(stdout); + len = 0; + return; } if (len + 1 >= size) { size += 128; buf = (char*)realloc(buf, size); } - buf[len++] = v; + if (v >= ' ') + buf[len++] = v; } void avr_set_console_register(avr_t * avr, avr_io_addr_t addr) @@ -285,6 +289,7 @@ extern avr_kind_t tiny13; extern avr_kind_t tiny2313; extern avr_kind_t tiny25,tiny45,tiny85; extern avr_kind_t tiny24,tiny44,tiny84; +extern avr_kind_t mega8; extern avr_kind_t mega48,mega88,mega168,mega328; extern avr_kind_t mega164,mega324,mega644; extern avr_kind_t mega128; @@ -294,6 +299,7 @@ avr_kind_t * avr_kind[] = { &tiny2313, &tiny25, &tiny45, &tiny85, &tiny24, &tiny44, &tiny84, + &mega8, &mega48, &mega88, &mega168, &mega328, &mega164, &mega324, &mega644, &mega128, -- 2.20.1