From 6e736328bd5abcb74cb7baac981d1a1dbb6d21b9 Mon Sep 17 00:00:00 2001 From: Dobrica Pavlinusic Date: Fri, 5 Jun 2015 23:09:59 +0200 Subject: [PATCH] correct pinout for protoboard --- AD9850/AD9850.ino | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/AD9850/AD9850.ino b/AD9850/AD9850.ino index a3b9d19..0ddf560 100644 --- a/AD9850/AD9850.ino +++ b/AD9850/AD9850.ino @@ -7,10 +7,10 @@ * Use freely */ -#define W_CLK 6 // connect to AD9850 module word load clock pin (CLK) -#define FQ_UD 5 // connect to freq update pin (FQ) -#define DATA 4 // connect to serial data load pin (DATA) -#define RESET 3 // connect to reset pin (RST). +#define W_CLK 7 // connect to AD9850 module word load clock pin (CLK) +#define FQ_UD 6 // connect to freq update pin (FQ) +#define DATA 5 // connect to serial data load pin (DATA) +#define RESET 4 // connect to reset pin (RST). #define ENCODER 0 #define encoder_a 7 -- 2.20.1