From fed69cd4a0c0fd839f16ca975f72f42baaaf86b0 Mon Sep 17 00:00:00 2001 From: Harald Welte Date: Tue, 9 Nov 2010 18:19:06 +0100 Subject: [PATCH] add some header files about MTK GSM related peripherals --- src/target/firmware/include/mtk/bfe.h | 107 +++++++++++++++++++ src/target/firmware/include/mtk/bpi.h | 18 ++++ src/target/firmware/include/mtk/bsi.h | 41 +++++++ src/target/firmware/include/mtk/tdma_timer.h | 60 +++++++++++ 4 files changed, 226 insertions(+) create mode 100644 src/target/firmware/include/mtk/bfe.h create mode 100644 src/target/firmware/include/mtk/bpi.h create mode 100644 src/target/firmware/include/mtk/bsi.h create mode 100644 src/target/firmware/include/mtk/tdma_timer.h diff --git a/src/target/firmware/include/mtk/bfe.h b/src/target/firmware/include/mtk/bfe.h new file mode 100644 index 0000000..b07f620 --- /dev/null +++ b/src/target/firmware/include/mtk/bfe.h @@ -0,0 +1,107 @@ +#ifndef _MTK_BFE_H +#define _MTK_BFE_H + +/* MTK Baseband Frontend */ + +/* MT6235 Chapter 10 */ + +enum mtk_bfe_reg { + BFE_CON = 0x0000, + BFE_STA = 0x0004, + /* Rx Configuration Register */ + RX_CFG = 0x0010, + /* Rx Control Register */ + RX_CON = 0x0014, + /* RX Interference Detection Power Measurement Control Register */ + RX_PM_CON = 0x0018, + /* RX FIR Coefficient Set ID Control Register */ + RX_FIR_CSID_CON = 0x001c, + /* RX Ram0 Coefficient Set 0 Register */ + RX_RAM0_CS0 = 0x0070, + /* RX Ram1 Coefficient Set 0 Register */ + RX_RAM1_CS0 = 0x0020, + /* Rx Interference Detection HPF Power Register */ + RX_HPWR_STS = 0x00b0, + /* Rx Interference Detection BPF Power Register */ + RX_BPWR_STS = 0x00b4, + + TX_CFG = 0x0060, + TX_CON = 0x0064, + TX_OFF = 0x0068, +}; + +#define RX_RAM0_CS(n) (RX_RAM0_CS0 + (n)*4) +#define RX_RAM1_CS(n) (RX_RAM0_CS1 + (n)*4) + +/* SWAP I/Q before input to baesband frontend */ +#define RX_CFG_SWAP_IQ 0x0001 +/* Bypass RX FIR filter control */ +#define RX_CFG_BYPFLTR 0x0002 +/* Number of RX FIR filter taps */ +#define RX_CFG_FIRTPNO(n) (((n) & 0x3f) << 4) + +#define RX_CON_BLPEN_NORMAL (0 << 0) +#define RX_CON_BLPEN_LOOPB (1 << 0) +#define RX_CON_BLPEN_LOOPB_FILT (2 << 0) + +/* Phase de-rotation in wide FIR data path */ +#define RX_CON_PH_ROEN_W (1 << 2) +/* Phase de-rotation in narrow FIR data path */ +#define RX_CON_PH_ROEN_N (1 << 3) +/* RX I-data gain compenstation select (+/- 1.5dB */ +#define RX_CON_IGAINSEL_00dB (0 << 4) +#define RX_CON_IGAINSEL_03dB (1 << 4) +#define RX_CON_IGAINSEL_06dB (2 << 4) +#define RX_CON_IGAINSEL_09dB (3 << 4) +#define RX_CON_IGAINSEL_12dB (4 << 4) +#define RX_CON_IGAINSEL_15dB (5 << 4) +#define RX_CON_IGAINSEL_n03dB (9 << 4) +#define RX_CON_IGAINSEL_n06dB (10 << 4) +#define RX_CON_IGAINSEL_n09dB (11 << 4) +#define RX_CON_IGAINSEL_n12dB (12 << 4) +#define RX_CON_IGAINSEL_n15dB (13 << 4) + +/* TX_CFG */ +/* Appending Bits enable */ +#define TX_CFG_APNDEN (1 << 0) +/* Ramp Profile Select for 8PSK */ +#define TX_CFG_RPSEL_I (0 << 1) /* 50 kHz sine tone */ +#define TX_CFG_RPSEL_II (1 << 1) /* null DC I/Q */ +#define TX_CFG_RPSEL_III (3 << 1) +#define TX_CFG_INTEN (1 << 3) /* Interpolate between bursts */ +#define TX_CFG_MDBYP (1 << 4) /* Modulator Bypass */ +#define TX_CFG_SGEN (1 << 5) /* 540 kHz sine tone */ +#define TX_CFG_ALL_10GEN_ZERO (1 << 6) +#define TX_CFG_ALL_10GEN_ONE (2 << 6) +#define TX_CFG_SW_QBCNT(n) (((n) & 0x1f) << 8) +#define TX_CFG_GMSK_DTAP_SYM_1 (0 << 13) +#define TX_CFG_GMSK_DTAP_SYM_0 (1 << 13) +#define TX_CFG_GMSK_DTAP_SYM_2 (2 << 13) + +#define TX_CON_IQSWP (1 << 0) /* Swap I/Q */ +/* GMSK or 8PSK modulation for 1st through 4th burst */ +#define TX_CON_MDSEL1_8PSK (1 << 2) +#define TX_CON_MDSEL2_8PSK (1 << 3) +#define TX_CON_MDSEL3_8PSK (1 << 4) +#define TX_CON_MDSEL4_8PSK (1 << 5) +/* Quadratur phase compensation select */ +#define TX_CON_PHSEL_0deg (0 << 8) +#define TX_CON_PHSEL_1deg (1 << 8) +#define TX_CON_PHSEL_2deg (2 << 8) +#define TX_CON_PHSEL_3deg (3 << 8) +#define TX_CON_PHSEL_4deg (4 << 8) +#define TX_CON_PHSEL_5deg (5 << 8) +#define TX_CON_PHSEL_n5deg (10 << 8) +#define TX_CON_PHSEL_n4deg (11 << 8) +#define TX_CON_PHSEL_n3deg (12 << 8) +#define TX_CON_PHSEL_n2deg (13 << 8) +#define TX_CON_PHSEL_n1deg (14 << 8) +/* GMSK modulator output latenct */ +#define TX_CON_GMSK_DTAP_QB(n) (((n) & 3) << 12) + +#define TX_OFF_I(n) (((n) & 0x3f) << 0) +#define TX_OFF_Q(n) (((n) & 0x3f) << 8) +/* Double Buffering */ +#define TX_OFF_TYP_DB 0x8000 + +#endif /* _MTK_BFE_H */ diff --git a/src/target/firmware/include/mtk/bpi.h b/src/target/firmware/include/mtk/bpi.h new file mode 100644 index 0000000..7328c15 --- /dev/null +++ b/src/target/firmware/include/mtk/bpi.h @@ -0,0 +1,18 @@ +#ifndef _MTK_BPI_H +#define _MTK_BPI_H + +/* MTK Baseband Parallel Interface */ + +/* Chapter 9.2 of MT6235 Data Sheet */ + +#define BPI_BUF(n) (BPI_BUF0 + ((n) * 4)) + +enum mtk_bpi_reg { + BPI_CON = 0x0000, + BPI_BUF0 = 0x0004, + BPI_ENA0 = 0x00b0, + BPI_ENA1 = 0x00b4, + BPI_ENA2 = 0x00b8, +}; + +#endif /* _MTK_BPI_H */ diff --git a/src/target/firmware/include/mtk/bsi.h b/src/target/firmware/include/mtk/bsi.h new file mode 100644 index 0000000..6f381ce --- /dev/null +++ b/src/target/firmware/include/mtk/bsi.h @@ -0,0 +1,41 @@ +#ifndef _MTK_BSI_H +#define _MTK_BSI_H + +/* MTK Baseband Serial Interface */ + +enum bsi_reg { + BSI_CON = 0x0000, + BSI_D0_CON = 0x0004, + BSI_D0_DAT = 0x0008, + + BSI_ENA_0 = 0x0190, + BSI_ENA_1 = 0x0194, + BSI_IO_CON = 0x0198, + BSI_DOUT = 0x019c, + BSI_DIN = 0x01a0, + BSI_PAIR_NUM = 0x01a4, + +}; + +/* Compute offset of BSI_D0_CON / BSI_D0_DAT registers */ +#define BSI_Dn_CON(x) (BSI_D0_CON + (x * 8)) +#define BSI_Dn_CON(x) (BSI_D0_DAT + (x * 8)) + +/* MT6235 Section 9.1.1 */ +#define BSI_CON_CLK_POL_INV (1 << 0) +#define BSI_CON_CLK_SPD_52_2 (0 << 1) /* 26 MHz */ +#define BSI_CON_CLK_SPD_52_4 (1 << 1) /* 13 MHz */ +#define BSI_CON_CLK_SPD_52_6 (2 << 1) /* 8.67 MHz */ +#define BSI_CON_CLK_SPD_52_8 (3 << 1) /* 6.50 MHz */ +#define BSI_CON_IMOD (1 << 3) +#define BSI_CON_EN0_LEN_SHORT (1 << 4) +#define BSI_CON_EN0_POL_INV (1 << 5) +#define BSI_CON_EN0_LEN_SHORT (1 << 6) +#define BSI_CON_EN0_POL_INV (1 << 7) +#define BSI_CON_SETENV (1 << 8) + +/* how the length is encoded in BSI_Dx_CON */ +#define BSI_Dx_LEN(n) ((n & 0x7f) << 8) +#define BSI_Dx_ISB 0x8000 /* select device 1 */ + +#endif /* _MTK_BSI_H */ diff --git a/src/target/firmware/include/mtk/tdma_timer.h b/src/target/firmware/include/mtk/tdma_timer.h new file mode 100644 index 0000000..dec0a8a --- /dev/null +++ b/src/target/firmware/include/mtk/tdma_timer.h @@ -0,0 +1,60 @@ +#ifndef _MTK_TDMA_H +#define _MTK_TDMA_H + +/* MTK TDMA Timer */ + +/* MT6235 Section 11 */ + +enum mtk_tdma_reg { + /* Read current quarter bit count */ + TDMA_TQCNT = 0x0000, + /* Latched Qbit counter reset position */ + TDMA_WRAP = 0x0004, + /* Direct Qbit counter reset position */ + TDMA_WRAPIMD = 0x0008, + /* Event latch position */ + TDMA_EVTVAL = 0x000c, + /* DSP software control */ + TDMA_DTIRQ = 0x0010, + /* MCU software control */ + TDMA_CTIRQ1 = 0x0014, + TDMA_CTIRQ2 = 0x0018, + /* AFC control */ + TDMA_AFC0 = 0x0020, + TDMA_AFC1 = 0x0024, + TDMA_AFC2 = 0x0028, + TDMA_AFC3 = 0x002c, + + /* BSI event */ + TDMA_BSI0 = 0x00b0, + /* BPI event */ + TDMA_BPI0 = 0x0100, + /* Auxiliary ADC event */ + TDMA_AUXEV0 = 0x0400, + TDMA_AUXEV1 = 0x0404, + /* Event Control */ + TDMA_EVTENA0 = 0x0150, + TDMA_EVTENA1 = 0x0154, + TDMA_EVTENA2 = 0x0158, + TDMA_EVTENA3 = 0x015c, + TDMA_EVTENA4 = 0x0160, + TDMA_EVTENA5 = 0x0164, + TDMA_EVTENA6 = 0x0168, + TDMA_EVTENA6 = 0x016c, + TDMA_WRAPOFS = 0x0170, + TDMA_REGBIAS = 0x0174, + TDMA_DTXCON = 0x0180, + TDMA_RXCON = 0x0184, + TDMA_BDLCON = 0x0188, + TDMA_BULCON1 = 0x018c, + TDMA_BULCON2 = 0x0190, + TDMA_FB_FLAG = 0x0194, + TDMA_FB_CLRI = 0x0198, +}; + +#define TDMA_BSI(n) (TDMA_BSI0 + (n)*4) +#define TDMA_BPI(n) (TDMA_BPI0 + (n)*4) + + + +#endif /* _MTK_TDMA_H */ -- 2.20.1